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data book 1 2.00 direct rdram 128/144-mbit (256k 16/18 32s) overview the rambus direct rdram ? is a general purpose high-performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. the 128/144-mbit direct rambus drams (rdram a ) are extremely high-speed cmos drams organized as 8m words by 16 or 18 bits. the use of rambus signaling level (rsl) technology permits 600 mhz to 800 mhz transfer rates while using conventional system and board design technologies. direct rdram devices are capable of sustained data transfers at 1.25 ns per two bytes (10 ns per sixteen bytes). the architecture of the direct rdrams allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. the separate control and data buses with independent row and column control yield over 95% bus efficiency. the direct rdram's thirty-two banks support up to four simultaneous transactions. system oriented features for mobile, graphics and large memory systems include power management, byte masking, and x18 organization. the two data bits in the x18 organization are general and can be used for additional storage and bandwidth or for error correction. features ? highest sustained bandwidth per dram device C 1.6 gb/s sustained data transfer rate C separate control and data buses for maximized efficiency C separate row and column control buses for easy scheduling and highest performance C 32 banks: four transactions can take place simultaneously at full bandwidth data rates ? low latency features C write buffer to reduce read latency C 3 precharge mechanisms for controller flexibility C interleaved transactions ? advanced power management: C multiple low power states allows flexibility in power consumption versus time to transition to active state C power-down self-refresh ? organization: 1 kbyte pages and 32 banks, x16/18 C x18 organization allows ecc configurations or increased storage/bandwidth C x16 organization for low cost applications ? uses rambus signaling level (rsl) for up to 800 mhz operation
direct rdram 128/144-mbit (256k 16/18 32s) data book 2 2.00 figure 1 direct rdram csp package the 128/144-mbit direct rdrams are offered in a csp horizontal package suitable for desktop as well as low-profile add-in card and mobile applications. direct rdrams operate from a 2.5 v supply. table 1 key timing parameters/part numbers organization i/o freq. mhz trac part number normal package: 8m 18 600 53 ns hyb25r144180c-653 8m 18 711 45 ns hyb25r144180c-745 8m 18 800 45 ns hyb25r144180c-845 8m 18 800 40 ns hyb25r144180c-840 8m 16 600 53 ns hyb25r128160c-653 8m 16 711 45 n s hyb25r128160c-745 8m 16 800 45 ns hyb25r128160c-845 8m 16 800 40 ns hyb25r128160c-840 mirror package: 8m 18 600 53 ns HYB25M144180C-653 8m 18 711 45 ns HYB25M144180C-745 8m 18 800 45 ns HYB25M144180C-845 8m 18 800 40 ns HYB25M144180C-840 8m 16 600 53 ns hyb25m128160c-653 8m 16 711 45 n s hyb25m128160c-745 8m 16 800 45 ns hyb25m128160c-845 8m 16 800 40 ns hyb25m128160c-840
data book 3 2.00 direct rdram 128/144-mbit (256k 16/18 32s) pinouts and definitions this tables show the pin assignments of the rdram package from the top-side of the package (the view looking down on the package as it is mounted on the circuit board). the mechanical dimensions of this package are shown in a later section. refer to section center-bonded fbga package on page 86. note - pin #1 is at the a1 position. dqa8/dqb8 are used for 144 mbit only. they are n.c. for 128mbit. table 2 normal package (top view) table 3 mirrored package (top view) 12 gnd C vdd CCC v dd C gnd 11 C CCCCCCCC 10 dqa7 dqa4 cfm cfmn rq5 rq3 dqb0 dqb4 dqb7 9 gnd v dd gnd gnda v dd gnd v dd v dd gnd 8 cmd dqa5 dqa2 v dda rq6 rq2 dqb1 dqb5 sio1 7 C CCCCCCCC 6 C CCCCCCCC 5 sck dqa6 dqa1 v ref rq7 rq1 dqb2 dqb6 sio0 4 v cmos gnd v dd gnd gnd v dd gnd gnd v cmos 3 dqa8 dqa3 dqa0 ctmn ctm rq4 rq0 dqb3 dqb8 2 C CCCCCCCC 1 gnd C v dd CCC v dd C gnd a bcdef ghj 12 gnd C vdd CCC v dd C gnd 11 C CCCCCCCC 10 dqa8 dqa3 dqa0 ctmn ctm rq4 rq0 dqb3 dqb8 9 v cmos gnd v dd gnd gnd v dd gnd gnd v cmos 8 sck dqa6 dqa1 v ref rq7 rq1 dqb2 dqb6 sio0 7 C CCCCCCCC 6 C CCCCCCCC 5 cmd dqa5 dqa2 v dda rq6 rq2 dqb1 dqb5 sio1 4 gnd v dd gnd gnda v dd gnd v dd v dd gnd 3 dqa7 dqa4 cfm cfmn rq5 rq3 dqb0 dqb4 dqb7 2 C CCCCCCCC 1 gnd C v dd CCC v dd C gnd a bcdef ghj
direct rdram 128/144-mbit (256k 16/18 32s) data book 4 2.00 table 4 signal i/o type # pins edge # pins center description sio1,sio0 i/o cmos 1) 1) all cmos signals are high-true; a high voltage is a logic one and a low voltage is logic zero. 2 2 serial input/output. pins for reading from and writing to the control registers using a serial access protocol. also used for power management. cmd i cmos 1) 1 1 command input. pins used in conjunction with sio0 and sio1 for reading from and writing to the control registers. also used for power management. sck i cmos 1) 1 1 serial clock input. clock source used for reading from and writing to the control registers. v dd CC 14 6 supply voltage for the rdram core and interface logic. v dda CC 2 1 supply voltage for the rdram analog circuitry. v cmos CC 2 2 supply voltage for cmos input/output pins. gnd CC 19 9 ground reference for rdram core and interface. gnda CC 2 1 ground reference for rdram analog circuitry. dqa8 dqa0 i/o rsl 2) 2) all rsl signals are low-true; a low voltage is a logic one and a high voltage is logic zero. 9 9 data byte a. nine pins which carry a byte of read or write data between the channel and the rdram. dqa8 is not used by rdrams with a x16 organization. cfm i rsl 2) 1 1 clock from master. interface clock used for receiving rsl signals from the channel. positive polarity. cfmn i rsl 2) 1 1 clock from master. interface clock used for receiving rsl signals from the channel. negative polarity v ref 1 1 logic threshold reference voltage for rsl signals ctmn i rsl 2) 1 1 clock to master. interface clock used for transmitting rsl signals to the channel. negative polarity. ctm i rsl 2) 1 1 clock to master. interface clock used for transmitting rsl signals to the channel. positive polarity. rq7 rq5 or row2 row0 irsl 2) 3 3 row access control. three pins containing control and address information for row accesses. rq4 rq0 or col4 col0 irsl 2) 5 5 column access control. five pins containing control and address information for column accesses. dqb8 dqb0 i/o rsl 2) 9 9 data byte b. nine pins which carry a byte of read or write data between the channel and the rdram. dqb8 is not used by rdrams with a x16 organization. total pin count per package 74 54 C
data book 5 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 2 128/144-mbit direct rdram block diagram spb04206 1:8 demux packet decode rowa rowr 11 5 5 9 tclk control registers rclk ctm ctmn rclk cfm cfmn 8 packet decode colc 5 5 colm 8 6 5 colx 6 5 5 xopm dx xop decode match match write buffer mux mux column decode & mask match mux row decode 1:8 demux rclk power modes devid refr 1:8 demux rclk write buffer 9 bank 0 samp 0 0/1 samp bank 1 samp 1/2 bank 2 bank 13 samp 13/14 bank 14 samp 14/15 bank 15 samp 15 bank 16 samp 16/17 bank 17 samp 17/18 bank 18 samp bank 29 samp 29/30 bank 30 samp 30/31 bank 31 samp 31 bx cops dc bc c mb ma r br dr ropav prer act prex rd, wr samp 0 samp 0/1 samp 1/2 samp 13/14 samp 14/15 samp 15 samp 16/17 samp 17/18 samp 16 samp 29/30 samp 30/31 samp 31 9 8:1 mux 9 9 1:8 demux write buffer 8:1 mux 9 9 9 9 9 9 72 72 sense amp 32 x 72 32 x 72 32 x 72 dram core 512 x 64 x 144 3 9 dqb8...dqb0 row2...row0 rq7...rq5 or 2 2 rq4...rq0 or col4...col0 5 dqa8...dqa0 9 dm tclk rclk tclk internal dqb data path internal dqa data path 16 sck, cmd sio0, sio1
direct rdram 128/144-mbit (256k 16/18 32s) data book 6 2.00 general description figure 2 is a block diagram of the 128/144 mbit direct rdram. it consists of two major blocks: a core block built from banks and sense amps similar to those found in other types of dram, and a direct rambus interface block which permits an external controller to access this core at up to 1.6 gb/s. control registers : the cmd, sck, sio0, and sio1 pins appear in the upper center of figure 2 . they are used to write and read a block of control registers. these registers supply the rdram configuration information to a controller and they select the operating modes of the device. the nine bit refr value is used for tracking the last refreshed row. most importantly, the five bit devid specifies the device address of the rdram on the channel. clocking : the ctm and ctmn pins (clock-to-master) generate tclk (transmit clock), the internal clock used to transmit read data. the cfm and cfmn pins (clock-from-master) generate rclk (receive clock), the internal clock signal used to receive write data and to receive the row and col pins. dqa, dqb pins : these 18 pins carry read (q) and write (d) data across the channel. they are multiplexed/de-multiplexed from/to two 72-bit data paths (running at one-eighth the data frequency) inside the rdram. banks : the 16 mbyte core of the rdram is divided into 32 0.5 mbyte banks, each organized as 512 rows, with each row containing 64 dualocts, and each dualoct containing 16 bytes. a dualoct is the smallest unit of data that can be addressed. sense amps : the rdram contains 34 sense amps. each sense amp consists of 512 bytes of fast storage (256 for dqa and 256 for dqb) and can hold one-half of one row of one bank of the rdram. the sense amp may hold any of the 512 half-rows of an associated bank. however, each sense amp is shared between two adjacent banks of the rdram (except for numbers 0, 15, 30, and 31). this introduces the restriction that adjacent banks may not be simultaneously accessed. rq pins : these pins carry control and address information. they are broken into two groups. rq7 rq5 are also called row2 row0, and are used primarily for controlling row accesses. rq4 rq0 are also called col4 col0, and are used primarily for controlling column accesses. row pins : the principle use of these three pins is to manage the transfer of data between the banks and the sense amps of the rdram. these pins are de-multiplexed into a 24-bit rowa (row-activate) or rowr (row-operation) packet. col pins : the principle use of these five pins is to manage the transfer of data between the dqa/dqb pins and the sense amps of the rdram. these pins are de-multiplexed into a 23-bit colc (column-operation) packet and either a 17-bit colm (mask) packet or a 17-bit colx (extended-operation) packet. act command : an act (activate) command from an rowa packet causes one of the 512 rows of the selected bank to be loaded to its associated sense amps (two 256 byte sense amps for dqa and two for dqb). prer command : a prer (precharge) command from an rowr packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be activated.
data book 7 2.00 direct rdram 128/144-mbit (256k 16/18 32s) rd command : the rd (read) command causes one of the 64 dualocts of one of the sense amps to be transmitted on the dqa/dqb pins of the channel. wr command : the wr (write) command causes a dualoct received from the dqa/dqb data pins of the channel to be loaded into the write buffer. there is also space in the write buffer for the bc bank address and c column address information. the data in the write buffer is automatically retired (written with optional bytemask) to one of the 64 dualocts of one of the sense amps during a subsequent cop command. a retire can take place during a rd, wr, or nocop to another device, or during a wr or nocop to the same device. the write buffer will not retire during a rd to the same device. the write buffer reduces the delay needed for the internal dqa/dqb data path turn- around. prec precharge : the prec, rda and wra commands are similar to nocop, rd and wr, except that a precharge operation is performed at the end of the column operation. these commands provide a second mechanism for performing precharge. prex precharge : after a rd command, or after a wr command with no byte masking (m = 0), a colx packet may be used to specify an extended operation (xop). the most important xop command is prex. this command provides a third mechanism for performing precharge. packet format figure 3 shows the formats of the rowa and rowr packets on the row pins. table 5 describes the fields which comprise these packets. dr4t and dr4f bits are encoded to contain both the dr4 device address bit and a framing bit which allows the rowa or rowr packet to be recognized by the rdram. the av (rowa/rowr packet selection) bit distinguishes between the two packet types. both the rowa and rowr packet provide a five bit device address and a five bit bank address. an rowa packet uses the remaining bits to specify a nine bit row address, and the rowr packet uses the remaining bits for an eleven bit opcode field. note the use of the rsvx notation to reserve bits for future address field extension. figure 3 also shows the formats of the colc, colm, and colx packets on the col pins. table 6 describes the fields which comprise these packets. table 5 field description for rowa packet and rowr packet field description dr4t, dr4f bits for framing (recognizing) a rowa or rowr packet. also encodes highest device address bit. dr3 dr0 device address for rowa or rowr packet. br4 br0 bank address for rowa or rowr packet. rsvb denotes bits ignored by the rdram. av selects between rowa packet (av = 1) and rowr packet (av = 0). r8 r0 row address for rowa packet. rsvr denotes bits ignored by the rdram. rop10 rop0 opcode field for rowr packet. specifies precharge, refresh, and power management functions.
direct rdram 128/144-mbit (256k 16/18 32s) data book 8 2.00 the colc packet uses the s (start) bit for framing. a colm or colx packet is aligned with this colc packet, and is also framed by the s bit. the 23 bit colc packet has a five bit device address, a five bit bank address, a six bit column address, and a four bit opcode. the colc packet specifies a read or write command, as well as some power management commands. the remaining 17 bits are interpreted as a colm (m = 1) or colx (m = 0) packet. a colm packet is used for a colc write command which needs bytemask control. the colm packet is associated with the colc packet from a time t rtr earlier. an colx packet may be used to specify an independent precharge command. it contains a five bit device address, a five bit bank address, and a five bit opcode. the colx packet may also be used to specify some housekeeping and power management commands. the colx packet is framed within a colc packet but is not otherwise associated with any other packet. table 6 field description for colc packet, colm packet, and colx packet field description s bit for framing (recognizing) a colc packet, and indirectly for framing colm and colx packets. dc4 dc0 device address for colc packet. bc4 bc0 bank address for colc packet. rsvb denotes bits reserved for future extension (controller drives 0s). c5 c0 column address for colc packet. rsvc denotes bits ignored by the rdram. cop3 cop0 opcode field for colc packet. specifies read, write, precharge, and power management functions. m selects between colm packet (m = 1) and colx packet (m = 0). ma7 ma0 bytemask write control bits. 1 = write, 0 = no-write. ma0 controls the earliest byte on dqa8 0. mb7 mb0 bytemask write control bits. 1 = write, 0 = no-write. mb0 controls the earliest byte on dqb8 0. dx4 dx0 device address for colx packet. bx4 bx0 bank address for colx packet. rsvb denotes bits reserved for future extension (controller drives 0s). xop4 xop0 opcode field for colx packet. specifies precharge, i ol control, and power management functions.
data book 9 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 3 packet formats prex (d0) msk (b1) colm packet t10 the colm is associated with a previous colc, and is aligned with the present colc, indicated by the start bit (s = 1) position. col0 a) col1 mb5 mb6 mb2 mb3 mb0 col2 col3 col4 ctm/cfm mb7 m = 1 ma6 mb4 mb1 ma4 ma2 s=1 a ma7 ma5 ma3 t8 col0 dc0 col1 col2 dc1 dc2 cop3 cop2 t9 cop0 cop1 the colx is aligned with the present colc, indicated by the start bit (s = 1) position. col0 b) col1 xop0 xop1 dx0 dx1 bx2 spb04207 s=1 m = 0 ma0 ma1 col2 col3 ctm/cfm col4 c0 bc0 bc3 t11 bc4 bc1 rsvb bc2 c1 c2 t12 dqa8...0 dqb8...0 bx1 bx0 xop2 xop3 dx2 dx3 bx3 bx4 xop4 dx4 b rsvb colx packet t13 t14 t15 rowa packet t2 colc packet t2 t0 col3 col4 dc3 dc4 ctm/cfm s = 1 t1 row1 row0 dr3 dr4f row2 ctm/cfm dr4t br2 dr0 dr1 br1 av=1 rsvb br4 rsvr dr2 br0 br3 rsvr t0 t1 dr2 dr0 dr1 c5 rsvc c3 c4 t3 col4...col0 row2...row0 ctm/cfm r3 r6 r7 r4 r0 r1 r8 r5 r2 row1 row0 dr3 dr4f ctm/cfm row2 dr4t prer c0 t packet wr b1 act a0 t2 t0 t1 t3 t4 t7 t5 t6 t8 t9 t14 t12 t10 t11 t13 t15 rop8 rop7 rop6 rsvb 4rsvb br2 br1 av=0 rop9 br3 br0 rop10 rop1 rop0 rop3 rop4 rop2 rop5 t3 t8 rowr packet t9 t10 t11
direct rdram 128/144-mbit (256k 16/18 32s) data book 10 2.00 field encoding summary table 7 shows how the six device address bits are decoded for the rowa and rowr packets. the dr4t and dr4f encoding merges a fifth device bit with a framing bit. when neither bit is asserted, the device is not selected. note that a broadcast operation is indicated when both bits are set. broadcast operation would typically be used for refresh and power management commands. if the device is selected, the dm (devicematch) signal is asserted and an act or rop command is performed. table 8 shows the encodings of the remaining fields of the rowa and rowr packets. an rowa packet is specified by asserting the av bit. this causes the specified row of the specified bank of this device to be loaded into the associated sense amps. an rowr packet is specified when av is not asserted. an 11 bit opcode field encodes a command for one of the banks of this device. the prer command causes a bank and its two associated sense amps to precharge, so another row or an adjacent bank may be activated. the refa (refresh-activate) command is similar to the act command, except the row address comes from an internal register refr, and refr is incremented at the largest bank address. the refp (refresh- precharge) command is identical to a prer command. the napr, naprc, pdnr, attn, and rlxr commands are used for managing the power dissipation of the rdram and are described in more detail in power state management on page 58. the tcen and tcal commands are used to adjust the output driver slew rate and they are described in more detail in current and temperature control on page 65. table 7 device field encodings for rowa packet and rowr packet dr4t dr4f device selection device match signal (dm) 1 1 all devices (broadcast) dm is set to 1 0 1 one device selected dm is set to 1 if {devid4 devid0} == {0, dr3 dr0} else dm is set to 0 1 0 one device selected dm is set to 1 if {devid4 devid0} == {1, dr3 dr0} else dm is set to 0 0 0 no packet present dm is set to 0
data book 11 2.00 direct rdram 128/144-mbit (256k 16/18 32s) table 9 shows the cop field encoding. the device must be in the attn power state in order to receive colc packets. the colc packet is used primarily to specify rd (read) and wr (write) commands. retire operations (moving data from the write buffer to a sense amp) happen automatically. see figure 17 for a more detailed description. the colc packet can also specify a prec command, which precharges a bank and its associated sense amps. the rda/wra commands are equivalent to combining rd/wr with a prec. rlxc (relax) performs a power mode transition. see power state management on page 58. table 8 rowa packet and rowr packet field encodings dm 1) av rop10rop0 field name command description 1098765432:0 0 - ------------ no operation. 1 1 row address act activate row r8 r0 of bank br4 br0 of device and move device to attn 2) . 10 1 1000x 3) x x 000 prer precharge bank br4 br0 of this device. 10000 1 1 0 0 x 000 refa refresh (activate) row refr8 refr0 of bank br3 br0 of device. increment refr if br4 br0 = 1111 (see figure 50 ). 10 10 10 1 0 0 x 000 refp precharge bank br4 br0 of this device after refa (see figure 50 ). 1 0 xx000 0 1 x 000 pdnr move this device into the powerdown (pdn) power state (see figure 47 ). 1 0 xx000 1 0 x 000 napr move this device into the nap (nap) power state (see figure 47 ). 1 0 xx000 1 1 x 000 naprc move this device into the nap (nap) power state conditionally. 1 0 xxxxxxx 0 000 attn 2) move this device into the attention (attn) power state (see figure 45 ). 1 0 xxxxxxx 1 000 rlxr move this device into the standby (stby) power state (see figure 46 ). 1 0 0000000x 001 tcal temperature calibrate this device (see figure 52 ). 1 0 0000000x 010 tcen temperature calibrate/enable this device (see figure 52 ). 1 0 00000000000noropno operation. 1) the dm (device match signal) value is determined by the dr4t,dr4f, dr3 dr0 field of the rowa and rowr packets. see table 7 . 2) the attn command does not cause a rlx-to-attn transition for a broadcast operation (dr4t/dr4f = 1/1). 3) an x entry indicates which commands may be combined. for instance, the three commands prer/naprc/rlxr may be specified in one rop value (011000111000).
direct rdram 128/144-mbit (256k 16/18 32s) data book 12 2.00 table 9 colc packet field encodings s dc4 dc0 (select device) 1) cop3 0 name command description 0 ---- ----- C no operation. 1 /= (devid4 0) ----- C retire write buffer of this device. 1 == (devid4 0) x000 2) nocop retire write buffer of this device. 1 == (devid4 0) x001 wr retire write buffer of this device, then write column c5 c0 of bank bc4 bc0 to write buffer. 1 == (devid4 0) x010 rsrv reserved, no operation. 1 == (devid4 0) x011 rd read column c5 c0 of bank bc4 bc0 of this device. 1 == (devid4 0) x100 prec retire write buffer of this device, then precharge bank bc4 bc0 (see figure 14 ). 1 == (devid4 0) x101 wra same as wr, but precharge bank bc4 bc0 after write buffer (with new data) is retired. 1 == (devid4 0) x110 rsrv reserved, no operation. 1 == (devid4 0) x111 rda same as rd, but precharge bank bc4 bc0 afterward. 1 == (devid4 0) 1xxx rlxc move this device into the standby (stby) power state (see figure 46 ). 1) /= means not equal, == means equal. 2) an x entry indicates which commands may be combined. for instance, the two commands wr/rlxc may be specified in one cop value (1001).
data book 13 2.00 direct rdram 128/144-mbit (256k 16/18 32s) table 10 shows the colm and colx field encodings. the m bit is asserted to specify a colm packet with two 8 bit bytemask fields ma and mb. if the m bit is not asserted, an colx is specified. it has device and bank address fields, and an opcode field. the primary use of the colx packet is to permit an independent prex (precharge) command to be specified without consuming control bandwidth on the row pins. it is also used for the cal (calibrate) and sam (sample) current control commands (see current and temperature control on page 65), and for the rlxx power mode command (see power state management on page 58). table 10 colm packet and colx packet field encodings m dx4 dx0 (selects device) xop4 0 name command description 1 ---- C msk mb/ma bytemasks used by wr/wra. 0 /= (devid4 0) C C no operation. 0 == (devid4 0) 00000 noxop no operation. 0 == (devid4 0) 1xxx0 1) 1) an x entry indicates which commands may be combined. for instance, the two commands prex/rlxx may be specified in one xop value (10010). prex precharge bank bx4 bx0 of this device (see figure 14 ). 0 == (devid4 0) x10x0 cal calibrate (drive) i ol current for this device (see figure 51 ). 0 == (devid4 0) x11x0 cal/sam calibrate (drive) and sample (update) i ol current for this device (see figure 51 ). 0 == (devid4 0) xxx10 rlxx move this device into the standby (stby) power state (see figure 46 ). 0 == (devid4 0) xxxx1 rsrv reserved, no operation.
direct rdram 128/144-mbit (256k 16/18 32s) data book 14 2.00 dq packet timing figure 4 shows the timing relationship of colc packets with d and q data packets. this document uses a specific convention for measuring time intervals between packets: all packets on the row and col pins (rowa, rowr, colc, colm, colx) use the trailing edge of the packet as a reference point, and all packets on the dqa/dqb pins (d and q) use the leading edge of the packet as a reference point. an rd or rda command will transmit a dualoct of read data q a time t cac later. this time includes one to five cycles of round-trip propagation delay on the channel. the t cac parameter may be programmed to a one of a range of values (7, 8, 9, 10, 11, or 12 t cycle ). the value chosen depends upon the number of rdram devices on the channel and the rdram timing bin. see figure 39 for more information. a wr or wra command will receive a dualoct of write data d a time t cwd later. this time does not need to include the round-trip propagation time of the channel since the colc and d packets are traveling in the same direction. when a q packet follows a d packet (shown in the left half of the figure), a gap ( t cac C t cwd ) will automatically appear between them because the t cwd value is always less than the t cac value. there will be no gap between the two colc packets with the wr and rd commands which schedule the d and q packets. when a d packet follows a q packet (shown in the right half of the figure), no gap is needed between them because the t cwd value is less than the t cac value. however, a gap of t cac C t cwd or greater must be inserted between the colc packets with the rd wr commands by the controller so the q and d packets do not overlap. figure 4 read (q) and write (d) data packet - timing for t cac = 7, 8, 9, 10, 11, or 12 t cycle dqa8...0 dqb8...0 q (y1) cac t q (b1) spa04208 cac t q (c1) d (d1) t25 t5 rd b1 this gap on the dqa/dqb pins appears automatically row0 row2... col4...col0 wr a1 ctm/cfm t0 t1 t2 t3 t4 - cwd t t cac t cwd t15 t10 t6 t7 t8 t9 t11 t12 t13 t14 t20 t17 t16 t18 t19 t22 t21 this gap on the col pins must be inserted by the controller rd c1 cac t t cwd - cwd t wr d1 t35 t30 t27 t26 t28 t29 t32 t31 t33 t34 t37 t36 t38 t39 t42 t41 t40 t43 t44 t47 t46 t45
data book 15 2.00 direct rdram 128/144-mbit (256k 16/18 32s) colm packet to d packet mapping figure 5 shows a write operation initiated by a wr command in a colc packet. if a subset of the 16 bytes of write data are to be written, then a colm packet is transmitted on the col pins a time t rtr after the colc packet containing the wr command. the m bit of the colm packet is set to indicate that it contains the ma and mb mask fields. note that this colm packet is aligned with the colc packet which causes the write buffer to be retired. see figure 17 for more details. if all 16 bytes of the d data packet are to be written, then no further control information is required. the packet slot that would have been used by the colm packet ( t rtr after the colc packet) is available to be used as an colx packet. this could be used for a prex precharge command or for a housekeeping command (this case is not shown). the m bit is not asserted in an colx packet and causes all 16 bytes of the previous wr to be written unconditionally. note that a rd command will never need a colm packet, and will always be able to use the colx packet option (a read operation has no need for the byte-write-enable control bits). figure 5 also shows the mapping between the ma and mb fields of the colm packet and bytes of the d packet on the dqa and dqb pins. each mask bit controls whether a byte of data is written (= 1) or not written (= 0).
direct rdram 128/144-mbit (256k 16/18 32s) data book 16 2.00 figure 5 mapping between colm packet and d packet for wr command the m bit of the colm packet is one. (= 0) of the indicated db bits when controls writing (= 1) or no writing each bit of the mb7...mb0 field the m bit of the colm packet is one. (= 0) of the indicated da bits when controls writing (= 1) or no writing each bit of the ma7...ma0 field when m = 0, all data bytes are when m = 1, the ma and mb writing unconditionally. individual data bytes. fields control writing of col0 col1 col2 col3 mb5 mb6 mb2 mb3 mb0 mb7 m = 1 ma6 mb4 mb1 ma4 ma2 da55 da46 da37 da28 da19 da10 da1 da64 dqa1 ma1 da9 dqa0 da0 ma0 ma5 da45 ma3 da27 da18 ma2 da36 ma4 spa04209 ma7 da63 da54 ma6 db16 db10 db9 da17 da16 mb1 mb0 dqa7 da7 dqa8 da8 ma0 dqb0 dqb1 db0 db1 dqb7 db7 mb7 mb2 mb5 mb4 mb3 mb6 da53 da52 da34 da25 da44 da35 da26 da45 da70 da61 da71 da62 db52 db46 db45 db28 db27 db18 db19 db36 db37 db34 db25 db44 db64 db63 db54 db55 db70 db61 t12 t19 colm packet a0 = {da, ba, ra} act a0 transaction a: wr t17 col4 ctm/cfm ma7 ma5 ma3 t18 dqa8...0 dqb8...0 col4...col0 row0 wr a1 t2 ctm/cfm row2... t1 t0 t7 t3 t4 t5 t6 t8 t9 t10 t11 act b0 prer a2 db17 a1 = {da, ba, ca1} ma1 t20 ctm/cfm dqb8 db8 t19 cwd t d (a1) rtr t msk (a1) retire (a1) a3 = {da, ba} db53 db35 db26 db45 d packet t20 t21 db71 db62 t22 t17 t14 t13 t15 t16 t19 t18 t20 t21 t24 t23 t22 t25 t26 t29 t28 t27 t30 t31 t34 t33 t32 t35 t36 t39 t37 t38 t40 t41 t46 t44 t42 t43 t45 t47
data book 17 2.00 direct rdram 128/144-mbit (256k 16/18 32s) row-to-row packet interaction figure 6 row-to-row packet interaction-timing figure 6 shows two packets on the row pins separated by an interval t rrdelay which depends upon the packet contents. no other row packets are sent to banks {ba, ba+1, ba-1} between packet a and packet b unless noted otherwise. table 11 summarizes the t rrdelay values for all possible cases. cases rr1 through rr4 show two successive act commands. in case rr1, there is no restriction since the act commands are to different devices. in case rr2, the t rr restriction applies to the same device with non-adjacent banks. cases rr3 and rr4 are illegal (as shown) since bank ba needs to be precharged. if a prer to ba, ba+1, or ba-1 is inserted, t rrdelay is t rc ( t ras to the prer command, and t rp to the next act). cases rr5 through rr8 show an act command followed by a prer command. in cases rr5 and rr6, there are no restrictions since the commands are to different devices or to non-adjacent banks of the same device. in cases rr7 and rr8, the t ras restriction means the activated bank must wait before it can be precharged. cases rr9 through rr12 show a prer command followed by an act command. in cases rr9 and rr10, there are essentially no restrictions since the commands are to different devices or to non-adjacent banks of the same device. rr10a and rr10b depend upon whether a bracketed bank (ba 1) is precharged or activated. in cases rr11 and rr12, the same and adjacent banks must all wait t rp for the sense amp and bank to precharge before being activated. transaction b: ropb transaction a: ropa dqb8...0 dqa8...0 b0 = {db, bb, rb} a0 = {da, ba, ra} spt04210 col4...col0 row2... ctm/cfm ropa a0 t0 t1 t3 t2 t4 t17 t11 ropb b0 t8 rrdelay t t5 t6 t7 t9 t10 t14 t12 t13 t15 t16 t18 t19 row0
direct rdram 128/144-mbit (256k 16/18 32s) data book 18 2.00 row-to-row interaction (contd) cases rr13 through rr16 summarize the combinations of two successive prer commands. in case rr13 there is no restriction since two devices are addressed. in rr14, t pp applies, since the same device is addressed. in rr15 and rr16, the same bank or an adjacent bank may be given repeated prer commands with only the t pp restriction. two adjacent banks cant be activate simultaneously. a precharge command to one bank will thus affect the state of the adjacent banks (and sense amps). if bank ba is activate and a prer is directed to ba, then bank ba will be precharged along with sense amps ba-1/ba and ba/ba+1. if bank ba+1 is activate and a prer is directed to ba, then bank ba+1 will be precharged along with sense amps ba/ba+1 and ba+1/ba+2. if bank ba-1 is activate and a prer is directed to ba, then bank ba-1 will be precharged along with sense amps ba/ba-1 and ba-1/ba-2. a row packet may contain commands other than act or prer. the refa and refp commands are equivalent to act and prer for interaction analysis purposes. the interaction rules of the napr, naprc, pdnr, rlxr, attn, tcal, and tcen commands are discussed in later sections (see table 8 for cross-ref). table 11 row-to-row packet interaction - rules case # ropa da ba ra ropb db bb rb t rrdelay example rr1 act da ba ra act /= da xxxx xx t packet figure 11 rr2 act da ba ra act == da /= {ba, ba+1, ba-1} xx t rr figure 11 rr3 act da ba ra act == da == {ba+1, ba-1} xx t rc - illegal unless prer to ba/ba+1/ba-1 figure 10 rr4 act da ba ra act == da == {ba} xx t rc - illegal unless prer to ba/ba+1/ba-1 figure 10 rr5 act da ba ra prer /= da xxxx xx t packet figure 11 rr6 act da ba ra prer == da /= {ba, ba+1, ba-1} xx t packet figure 11 rr7 act da ba ra prer == da == {ba+1, ba-1} xx t ras figure 10 rr8 act da ba ra prer == da == {ba} xx t ras figure 15 rr9 prer da ba ra act /= da xxxx xx t packet figure 12 rr10 prer da ba ra act == da /= {ba, ba1, ba2} xx t packet figure 12 rr10a prer da ba ra act == da == {ba+2} xx t packet / t rp if ba+1 is precharged/activated. C rr10b prer da ba ra act == da == {ba-2} xx t packet / t rp if ba-1 is precharged/activated. C rr11 prer da ba ra act == da == {ba+1, ba-1} xx t rp figure 10 rr12 prer da ba ra act == da == {ba} xx t rp figure 10 rr13 prer da ba ra prer /= da xxxx xx t packet figure 12 rr14 prer da ba ra prer == da /= {ba, ba+1, ba-1} xx t pp figure 12 rr15 prer da ba ra prer == da == {ba+1, ba-1} xx t pp figure 12 rr16 prer da ba ra prer == da == ba xx t pp figure 12
data book 19 2.00 direct rdram 128/144-mbit (256k 16/18 32s) row-to-col packet interaction figure 7 shows two packets on the row and col pins. they must be separated by an interval t rcdelay which depends upon the packet contents. table 12 summarizes the t rcdelay values for all possible cases. note that if the col packet is earlier than the row packet, it is considered a col-to-row packet interaction. cases rc1 through rc5 summarize the rules when the row packet has an act command. figure 15 and figure 16 show examples of rc5 - an activation followed by a read or write. rc4 is an illegal situation, since a read or write of a precharged banks is being attempted (remember that for a bank to be activated, adjacent banks must be precharged). in cases rc1, rc2, and rc3, there is no interaction of the row and col packets. figure 7 row-to-col packet interaction - timing cases rc6 through rc8 summarize the rules when the row packet has a prer command. there is either no interaction (rc6 through rc9) or an illegal situation with a read or write of a precharged bank (rc9). the col pins can also schedule a precharge operation with a rda, wra, or prec command in a colc packet or a prex command in a colx packet. the constraints of these precharge operations may be converted to equivalent prer command constraints using the rules summarized in figure 14 . transaction b: copb transaction a: ropa dqb8...0 dqa8...0 b1 = {db, bb, cb1} a0 = {da, ba, ra} spt04211 col4...col0 row2... ctm/cfm copb b1 t0 t1 t3 t2 t4 t17 t11 ropa a0 t8 rcdelay t t5 t6 t7 t9 t10 t14 t12 t13 t15 t16 t18 t19 row0
direct rdram 128/144-mbit (256k 16/18 32s) data book 20 2.00 col-to-col packet interaction figure 8 col-to-col packet interaction-timing figure 8 shows three arbitrary packets on the col pins. packets b and c must be separated by an interval t ccdelay which depends upon the command and address values in all three packets. table 13 summarizes the t ccdelay values for all possible cases. cases cc1 through cc5 summarize the rules for every situation other than the case when copb is a wr command and copc is a rd command. in cc3, when a rd command is followed by a wr command, a gap of t cac C t cwd must be inserted between the two col packets. see figure 4 for more explanation of why this gap is needed. for cases cc1, cc2, cc4, and cc5, there is no restriction ( t ccdelay is t cc ). table 12 row-to-col packet interaction - rules case # ropa da ba ra copb db bb cb1 t rcdelay example rc1 act da ba ra nocop, rd, retire /= da xxxx xx 0 C rc2 act da ba ra nocop == da xxxx xx 0 C rc3 act da ba ra rd, retire == da /= {ba, ba+1, ba-1} xx 0 C rc4 act da ba ra rd, retire == da == {ba+1, ba-1} xx illegal C rc5 act da ba ra rd, retire == da == ba xx t rcd figure 15 rc6 prer da ba ra nocop, rd, retire /= da xxxx xx 0 C rc7 prer da ba ra nocop == da xxxx xx 0 C rc8 prer da ba ra rd, retire == da /= {ba, ba+1, ba-1} xx 0 C rc9 prer da ba ra rd, retire == da == {ba+1, ba-1} xx illegal C transaction b: copb transaction a: copa dqb8...0 dqa8...0 b1 = {db, bb, cb1} a1 = {da, ba, ca1} spt04212 col4...col0 row2... ctm/cfm t0 t1 t3 t2 t4 t17 t11 t8 ccdelay t t5 t6 t7 t9 t10 t14 t12 t13 t15 t16 t18 t19 row0 transaction c: copc c1 = {dc, bc, cc1} copa a1 copb b1 copc c1
data book 21 2.00 direct rdram 128/144-mbit (256k 16/18 32s) in cases cc6 through cc10, copb is a wr command and copc is a rd command. the t ccdelay value needed between these two packets depends upon the command and address in the packet with copa. in particular, in case cc6 when there is wr-wr-rd command sequence directed to the same device, a gap will be needed between the packets with copb and copc. the gap will need a colc packet with a nocop command directed to any device in order to force an automatic retire to take place. figure 18 (right) provides a more detailed explanation of this case. in case cc10, there is a rd-wr-rd sequence directed to the same device. if a prior write to the same device is unretired when copa is issued, then a gap will be needed between the packets with copb and copc as in case cc6. the gap will need a colc packet with a nocop command directed to any device in order to force an automatic retire to take place. cases cc7, cc8, and cc9 have no restriction ( t ccdelay is t cc ). for the purposes of analyzing col-to-row interactions, the prec, wra, and rda commands of the colc packet are equivalent to the nocop, wr, and rd commands. these commands also cause a precharge operation prec to take place. this precharge may be converted to an equivalent prer command on the row pins using the rules summarized in figure 14 . table 13 col-to-col packet interaction - rules case # copa da ba ca1 copb db bb cb1 copc dc bc cc1 t ccdelay example cc1 xxxx xxxxx xx xx nocop db bb cb1 xxxx xxxxx xx xx t cc C cc2 xxxx xxxxx xx xx rd,wr db bb cb1 nocop xxxxx xx xx t cc C cc3 xxxx xxxxx xx xx rd db bb cb1 wr xxxxx xx xx t cc + t cac - t cwd figure 4 cc4 xxxx xxxxx xx xx rd db bb cb1 rd xxxxx xx xx t cc figure 15 cc5 xxxx xxxxx xx xx wr db bb cb1 wr xxxxx xx xx t cc figure 16 cc6 wr == db x xx wr db bb cb1 rd == db xx xx t rtr figure 18 cc7 wr == db x xx wr db bb cb1 rd /= db xx xx t cc C cc8 wr /= db x xx wr db bb cb1 rd == db xx xx t cc C cc9 nocop == db x xx wr db bb cb1 rd == db xx xx t cc C cc10 rd == db x xx wr db bb cb1 rd == db xx xx t cc C
direct rdram 128/144-mbit (256k 16/18 32s) data book 22 2.00 col-to-row packet interaction figure 9 col-to-row packet interaction - timing figure 9 shows arbitrary packets on the col and row pins. they must be separated by an interval t crdelay which depends upon the command and address values in the packets. table 14 summarizes the t crdelay value for all possible cases. cases cr1, cr2, cr3, and cr9 show no interaction between the col and row packets, either because one of the commands is a nop or because the packets are directed to different devices or to non-adjacent banks. case cr4 is illegal because an already-activated bank is to be re-activated without being precharged case cr5 is illegal because an adjacent bank cant be activated or precharged until bank ba is precharged first. in case cr6, the colc packet contains a rd command, and the row packet contains a prer command for the same bank. the t rdp parameter specifies the required spacing. likewise, in case cr7, the colc packet causes an automatic retire to take place, and the row packet contains a prer command for the same bank. the t rtp parameter specifies the required spacing. case cr8 is labeled hazardous because a wr command should always be followed by an automatic retire before a precharge is scheduled. figure 19 shows an example of what can happen when the retire is not able to happen before the precharge. for the purposes of analyzing col-to-row interactions, the prec, wra, and rda commands of the colc packet are equivalent to the nocop, wr, and rd commands. these commands also cause a precharge operation to take place. this precharge may converted to an equivalent prer command on the row pins using the rules summarized in figure 14 . a row packet may contain commands other than act or prer. the refa and refp commands are equivalent to act and prer for interaction analysis purposes. the interaction rules of the napr, pdnr, and rlxr commands are discussed in a later section. transaction b: ropb transaction a: copa dqb8...0 dqa8...0 b0 = {db, bb, rb} a1 = {da, ba, ca1} spt04213 col4...col0 row2... ctm/cfm copa a1 t0 t1 t3 t2 t4 t17 t11 ropb b0 t8 crdelay t t5 t6 t7 t9 t10 t14 t12 t13 t15 t16 t18 t19 row0
data book 23 2.00 direct rdram 128/144-mbit (256k 16/18 32s) table 14 col-to-row packet interaction - rules case # copa da ba ca1 ropb db bb rb t crdelay example cr1 nocop da ba ca1 xx xxxxx xxxx xx 0 C cr2 rd/wr da ba ca1 xx /= da xxxx xx 0 C cr3 rd/wr da ba ca1 xx == da /= {ba, ba+1, ba-1} xx 0 C cr4 rd/wr da ba ca1 act == da == {ba} xx illegal C cr5 rd/wr da ba ca1 act == da == {ba+1, ba-1} xx illegal C cr6 rd da ba ca1 prer == da == {ba, ba+1, ba-1} xx t rdp figure 15 cr7 retire 1) da ba ca1 prer == da == {ba, ba+1, ba-1} xx t rtp figure 16 cr8 wr 2) da ba ca1 prer == da == {ba, ba+1, ba-1} xx 0 figure 19 cr9 xxxx da ba ca1 norop xxxxx xxxx xx 0 C 1) this is any command which permits the write buffer of device da to retire (see table 9 ). ba is the bank address in the write buffer. 2) this situation is hazardous because the write buffer will be left unretired while the targeted bank is precharged. see figure 19 .
direct rdram 128/144-mbit (256k 16/18 32s) data book 24 2.00 row-to-row examples figure 10 shows examples of some of the row-to-row packet spacings from table 11 . a complete sequence of activate and precharge commands is directed to a bank. the rr8 and rr12 rules apply to this sequence. in addition to satisfying the t ras and t rp timing parameters, the separation between act commands to the same bank must also satisfy the t rc timing parameter (rr4). when a bank is activated, it is necessary for adjacent banks to remain precharged. as a result, the adjacent banks will also satisfy parallel timing constraints; in the example, the rr11 and rr3 rules are analogous to the rr12 and rr4 rules. figure 10 row packet example figure 11 shows examples of the act-to-act (rr1, rr2) and act-to-prer (rr5, rr6) command spacings from table 11 . in general, the commands in row packets may be spaced an interval t packet apart unless they are directed to the same or adjacent banks or unless they are a similar command type (both prer or both act) directed to the same device. dqa8...0 dqb8...0 col4...col0 t rc spa04214 t24 same device same device same device same device same device row0 ctm/cfm row2... act a0 t2 t0 t1 t3 t4 t14 t7 t5 t6 t8 t9 t10 t11 t13 t12 ras t t19 t15 t16 t18 t17 t20 t21 t23 t22 a0 = {da, ba, ra} a1 = {da, ba+1} b0 = {da, ba+1, rb} b0 = {da, ba, rb} b0 = {da, ba+1, rb} b0 = {da, ba, rb} rr11 adjacent bank t34 rr12 act b0 prer a1 rp t t29 same bank t25 t26 t27 t28 t30 t31 t32 t33 t39 t36 t35 t37 t38 t41 t40 t42 t43 rr7 rr4 rr3 adjacent bank adjacent bank same bank t46 t45 t44 t47
data book 25 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 11 row packet example figure 12 shows examples of the prer-to-prer (rr13, rr14) and prer-to-act (rr9, rr10) command spacings from table 12 . the rr15 and rr16 cases (prer-to-prer to same or adjacent banks) are not shown, but are similar to rr14. in general, the commands in row packets may be spaced an interval t packet apart unless they are directed to the same or adjacent banks or unless they are a similar command type (both prer or both act) directed to the same device. dqa8...0 dqb8...0 col4...col0 spa04215 t24 different device same device same device different device act b0 row0 ctm/cfm row2... act a0 packet t t2 t0 t1 t3 t4 t14 act a0 t7 t5 t6 t8 t11 t13 t12 t act c0 rr t19 t15 t16 t18 t17 t20 t21 t23 t22 a0 = {da, ba, ra} b0 = {db, bb, rb} c0 = {da, bc, rc} b0 = {db, bb, rb} c0 = {da, bc, rc} any bank t34 non-adjacent bank prer b0 packet act a0 t t29 t27 t28 t30 t31 t32 t33 act a0 packet t t39 t36 t35 rr6 t41 t40 t42 t43 non-adjacent bank any bank rr1 rr5 rr2 prer c0 t46 t45 t44 t47
direct rdram 128/144-mbit (256k 16/18 32s) data book 26 2.00 figure 12 row packet examples row and column cycle description activate: a row cycle begins with the activate (act) operation. the activation process is destructive; the act of sensing the value of a bit in a banks storage cell transfers the bit to the sense amp, but leaves the original bit in the storage cell with an incorrect value. restore: because the activation process is destructive, a hidden operation called restore is automatically performed. the restore operation rewrites the bits in the sense amp back into the storage cells of the activated row of the bank. read/write: while the restore operation takes place, the sense amp may be read (rd) and written (wr) using column operations. if new data is written into the sense amp, it is automatically forwarded to the storage cells of the bank so the data in the activated row and the data in the sense amp remain identical. precharge: when both the restore operation and the column operations are completed, the sense amp and bank are precharged (pre). this leaves them in the proper state to begin another activate operation. intervals: the activate operation requires the interval t rcd,min to complete. the hidden restore operation requires the interval t ras,min C t rcd,min to complete. column read and write operations are also performed during the t ras,min C t rcd,min interval (if more than about four column operations are col4...col0 dqb8...0 dqa8...0 spa04216 t24 same device same device same device different device same device different device prer b0 row2... ctm/cfm row0 prer a0 packet t t2 t0 t1 t3 t4 t14 prer a0 t7 t5 t6 t8 t11 t13 t12 t prer c0 pp t19 t15 t16 t18 t17 t20 t21 t23 t22 c0 = {da, ba+1, rc} b0 = {db, bb, rb} c0 = {da, bc, rc} c0 = {da, ba, rc} c0 = {da, bc, rc} b0 = {db, bb, rb} a0 = {da, ba, ra} any bank t34 non-adjacent bank act b0 prer a0 packet t t29 t27 t28 t30 t31 t32 t33 prer a0 packet t t39 t36 t35 rr10 t41 t40 t42 t43 non-adjacent bank any bank same bank adjacent bank rr13 rr15 rr16 rr9 rr14 act c0 t46 t45 t44 t47
data book 27 2.00 direct rdram 128/144-mbit (256k 16/18 32s) performed, this interval must be increased). the precharge operation requires the interval t rp,min to complete. adjacent banks: an rdram with a s designation (256k 32s 16/18) indicates it contains split banks. this means the sense amps are shared between two adjacent banks. the only exception is that sense amp 0, 15, 30, and 31 are not shared. when a row in a bank is activated, the two adjacent sense amps are connected to (associated with) that bank and are not available for use by the two adjacent banks. these two adjacent banks must remain precharged while the selected bank goes through its activate, restore, read/write, and precharge operations. for example (referring to the block diagram of figure 2 ), if bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will both be loaded with one of the 512 rows (with 512 bytes loaded into each sense amp from the 1 kbyte row - 256 bytes to the dqa side and 256 bytes to the dqb side). while this row from bank 5 is being accessed, no rows may be accessed in banks 4 or 6 because of the sense amp sharing. precharge mechanisms figure 13 shows an example of precharge with the rowr packet mechanism. the prer command must occur a time t ras after the act command, and a time t rp before the next act command. this timing will serve as a baseline against which the other precharge mechanisms can be compared. figure 13 precharge via prer command in rowr packet figure 14 (top) shows an example of precharge with a rda command. a bank is activated with an rowa packet on the row pins. then, a series of four dualocts are read with rd commands in colc packets on the col pins. the fourth of these commands is a rda, which causes the bank to automatically precharge when the final read has finished. the timing of this automatic precharge is equivalent to a prer command in an rowr packet on the row pins that is offset a time t offp spa04217 t24 row2... col4...col0 dqb8...0 dqa8...0 rp t ctm/cfm t2 t1 t0 t3 t4 t14 t7 t5 t6 t8 t9 t12 t10 t11 t13 t19 t17 t15 t16 t18 t20 t21 t23 t22 t44 t34 t29 t25 t26 t28 t27 t30 t31 t33 t32 t39 t35 t36 t37 t38 t40 t41 t42 t43 t46 t45 t47 act a0 act b0 prer a5 row0 ras t t rc a0 = {da, ba, ra} a5 = {da, ba} b0 = {da, ba, rb}
direct rdram 128/144-mbit (256k 16/18 32s) data book 28 2.00 from the colc packet with the rda command. the rda command should be treated as a rd command in a colc packet as well as a simultaneous (but offset) prer command in an rowr packet when analyzing interactions with other packets. figure 14 (middle) shows an example of precharge with a wra command. as in the rda example, a bank is activated with an rowa packet on the row pins. then, two dualocts are written with wr commands in colc packets on the col pins. the second of these commands is a wra, which causes the bank to automatically precharge when the final write has been retired. the timing of this automatic precharge is equivalent to a prer command in an rowr packet on the row pins that is offset a time t offp from the colc packet that causes the automatic retire. the wra command should be treated as a wr command in a colc packet as well as a simultaneous (but offset) prer command in an rowr packet when analyzing interactions with other packets. note that the automatic retire is triggered by a colc packet a time t rtr after the colc packet with the wr command unless the second colc contains a rd command to the same device. this is described in more detail in figure 17 . figure 14 (bottom) shows an example of precharge with a prex command in an colx packet. a bank is activated with an rowa packet on the row pins. then, a series of four dualocts are read with rd commands in colc packets on the col pins. the fourth of these colc packets includes an colx packet with a prex command. this causes the bank to precharge with timing equivalent to a prer command in an rowr packet on the row pins that is offset a time t offp from the colx packet with the prex command.
data book 29 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 14 offsets for alternate precharge mechanisms d (a2) a1 = {da, ba, ca1} retire (a2) msk (a2) t24 prex a5 a1 = {da, ba, ca1} a3 = {da, ba, ca3} transaction a: rd dqb8...0 dqa8...0 a0 = {da, ba, ra} q (a1) transaction a: wr colc packet: prex precharge offset the prex precharge is equivalent to a prer command here ctm/cfm row0 col4...col0 row2... act a0 t2 t0 t1 t3 t4 col4...col0 dqb8...0 dqa8...0 t14 rd a2 rd a1 t7 t5 t6 t8 t9 t10 t11 t13 t12 rd a3 rd a4 t19 t15 t16 t18 t17 t20 t21 t23 t22 a0 = {da, ba, ra} d (a1) retire (a1) msk (a1) rtr t a5 = {da, ba} q (a4) a2 = {da, ba, ca2} a4 = {da, ba, ca4} q (a2) q (a3) spa04218 a5 = {da, ba} t34 act b0 prer a5 offp t t29 t25 t26 t27 t28 t30 t31 t32 t33 t39 t36 t35 t37 t38 t41 t40 t42 t43 a2 = {da, ba, ca2} offp t t46 t45 t44 t47 t24 t24 a1 = {da, ba, ca1} a3 = {da, ba, ca3} the wra precharge (triggered by the automatic retire) is equivalent to a prer command here transaction a: rd colc packet: wra precharge offset the rda precharge is equivalent to a prer command here row2... row0 ctm/cfm act a0 t2 t0 t1 t3 t4 row2... row0 dqb8...0 dqa8...0 col4...col0 act a0 t14 a0 = {da, ba, ra} t7 t5 t6 t8 t9 t10 t11 t13 t12 t19 t15 t16 t18 t17 t20 t21 t23 t22 rd a2 rd a1 rd a3 rd a4 q (a1) colc packet: rda precharge offset ctm/cfm t2 t0 t1 t3 t4 t14 t7 t5 t6 t8 t9 t10 t11 t13 t12 t19 t15 t16 t18 t17 t20 t21 t23 t22 a5 = {da, ba} t34 act b0 a2 = {da, ba, ca2} a4 = {da, ba, ca4} prer a5 t29 t25 t26 t27 t28 t30 t31 t32 t33 t39 t36 t35 t37 t38 t41 t40 t42 t43 act b0 q (a4) q (a2) q (a3) prer a5 offp t t46 t45 t44 t47 t34 t29 t25 t26 t27 t28 t30 t31 t32 t33 t39 t36 t35 t37 t38 t41 t40 t42 t43 t46 t45 t44 t47 wr a1 wra a2
direct rdram 128/144-mbit (256k 16/18 32s) data book 30 2.00 read transaction - example figure 15 shows an example of a read transaction. it begins by activating a bank with an act a0 command in an rowa packet. a time t rcd later a rd a1 command is issued in a colc packet. note that the act command includes the device, bank, and row address (abbreviated as a0) while the rd command includes device, bank, and column address (abbreviated as a1). a time t cac after the rd command the read data dualoct q(a1) is returned by the device. note that the packets on the row and col pins use the end of the packet as a timing reference point, while the packets on the dqa/dqb pins use the beginning of the packet as a timing reference point. a time t cc after the first colc packet on the col pins a second is issued. it contains a rd a2 command. the a2 address has the same device and bank address as the a1 address (and a0 address), but a different column address. a time t cac after the second rd command a second read data dualoct q(a2) is returned by the device. next, a prer a3 command is issued in an rowr packet on the row pins. this causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. the a3 address includes the same device and bank address as the a0, a1, and a2 addresses. the prer command must occur a time t ras or more after the original act command (the activation operation in any dram is destructive, and the contents of the selected row must be restored from the two associated sense amps of the bank during the t ras interval). the prer command must also occur a time t rdp or more after the last rd command. note that the t rdp value shown is greater than the t rdp,min specification in table 23 . this transaction example reads two dualocts, but there is actually enough time to read three dualocts before t rdp becomes the limiting parameter rather than t ras . if four dualocts were read, the packet with prer would need to shift right (be delayed) by one t cycle (note - this case is not shown). finally, an act b0 command is issued in an rowr packet on the row pins. the second act command must occur a time t rc or more after the first act command and a time t rp or more after the prer command. this ensures that the bank and its associated sense amps are precharged. this example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. transaction b may not be started until transaction a has finished. however, transactions to other banks or other devices may be issued during transaction a
data book 31 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 15 read transaction example write transaction - example figure 16 shows an example of a write transaction. it begins by activating a bank with an act a0 command in an rowa packet. a time t rcd C t rtr later a wr a1 command is issued in a colc packet (note that the t rcd interval is measured to the end of the colc packet with the first retire command). note that the act command includes the device, bank, and row address (abbreviated as a0) while the wr command includes device, bank, and column address (abbreviated as a1). a time t cwd after the wr command the write data dualoct d(a1) is issued. note that the packets on the row and col pins use the end of the packet as a timing reference point, while the packets on the dqa/dqb pins use the beginning of the packet as a timing reference point. a time t cc after the first colc packet on the col pins a second colc packet is issued. it contains a wr a2 command. the a2 address has the same device and bank address as the a1 address (and a0 address), but a different column address. a time t cwd after the second wr command a second write data dualoct d(a2) is issued. a time t rtr after each wr command an optional colm packet msk (a1) is issued, and at the same time a colc packet is issued causing the write buffer to automatically retire. see figure 17 for more detail on the write/retire mechanism. if a colm packet is not used, all data bytes are unconditionally written. if the colc packet which causes the write buffer to retire is delayed, then the colm packet (if used) must also be delayed. next, a prer a3 command is issued in an rowr packet on the row pins. this causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. the a3 address includes the same device and bank address as the a0, a1, and a2 addresses. the prer command must occur a time t ras or more after the original a1 = {da, ba, ca1} transaction b: xx transaction a: rd dqa8...0 dqb8...0 t b0 = {da, ba, rb} a0 = {da, ba, ra} rcd t t cac cc q (a1) t cac t rdp a3 = {da, ba} a2 = {da, ba, ca2} q (a2) spt04219 t24 row2... ctm/cfm row0 col4...col0 act a0 t2 t0 t1 t3 t4 rd a2 rd a1 ras t t rc t14 t7 t5 t6 t8 t9 t10 t11 t13 t12 t19 t15 t16 t18 t17 t20 t21 t23 t22 act b0 prer a3 t34 t29 t25 t26 t27 t28 t30 t31 t32 t33 t39 t36 t35 t37 t38 t41 t40 t42 t43 t46 t45 t44 t47
direct rdram 128/144-mbit (256k 16/18 32s) data book 32 2.00 act command (the activation operation in any dram is destructive, and the contents of the selected row must be restored from the two associated sense amps of the bank during the t ras interval). a prer a3 command is issued in an rowr packet on the row pins. the prer command must occur a time t rtp or more after the last colc which causes an automatic retire. finally, an act b0 command is issued in an rowr packet on the row pins. the second act command must occur a time t rc or more after the first act command and a time t rp or more after the prer command. this ensures that the bank and its associated sense amps are precharged. this example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. transaction b may not be started until transaction a has finished. however, transactions to other banks or other devices may be issued during transaction a. figure 16 write transaction example d (a2) msk (a2) retire (a2) a1 = {da, ba, ca1} transaction a: wr transaction b: xx dqb8...0 dqa8...0 col4...col0 t wr a2 a0 = {da, ba, ra} b0 = {da, ba, rb} wr a1 d (a1) cwd retire (a1) msk (a1) t t cwd cc a3 = {da, ba} a2 = {da, ba, ca2} spt04220 t24 ctm/cfm row2... row0 act a0 t2 t0 t1 t3 t4 rcd t t rtr t rtr t ras t rc t14 t7 t5 t6 t8 t9 t10 t11 t13 t12 t19 t15 t16 t18 t17 t20 t21 t23 t22 act b0 prer a3 rtp t rp t t34 t29 t25 t26 t27 t28 t30 t31 t32 t33 t39 t36 t35 t37 t38 t41 t40 t42 t43 t46 t45 t44 t47
data book 33 2.00 direct rdram 128/144-mbit (256k 16/18 32s) write/retire - examples the process of writing a dualoct into a sense amp of an rdram bank occurs in two steps. the first step consists of transporting the write command, write address, and write data into the write buffer. the second step happens when the rdram automatically retires the write buffer (with an optional bytemask) into the sense amp. this two-step write process reduces the natural turn-around delay due to the internal bidirectional data pins. figure 17 (left) shows an example of this two step process. the first colc packet contains the wr command and an address specifying device, bank and column. the write data dualoct follows a time t cwd later. this information is loaded into the write buffer of the specified device. the colc packet which follows a time t rtr later will retire the write buffer. the retire will happen automatically unless (1) a colc packet is not framed (no colc packet is present and the s bit is zero), or (2) the colc packet contains a rd command to the same device. if the retire does not take place at time t rtr after the original wr command, then the device continues to frame colc packets, looking for the first that is not a rd directed to itself. a bytemask msk(a1) may be supplied in a colm packet aligned with the colc that retires the write buffer at time t rtr after the wr command. the memory controller must be aware of this two-step write/retire process. controller performance can be improved, but only if the controller design accounts for several side effects. figure 17 normal retire (left) and retire/read ordering (right) figure 17 (right) shows the first of these side effects. the first colc packet has a wr command which loads the address and data into the write buffer. the third colc causes an automatic retire of the write buffer to the sense amp. the second and fourth colc packets (which bracket the retire packet) contain rd commands with the same device, bank and column address as the original wr command. in other words, the same dualoct address that is written is read both before and after it is actually retired. the first rd returns the old dualoct value from the sense amp before it is overwritten. the second rd returns the new dualoct value that was just written. transaction b: rd transaction c: rd transaction a: wr dqa8...0 dqb8...0 transaction a: wr a1 = {da, ba, ca1} cwd t t rtr d (a1) dqa8...0 dqb8...0 d (a1) c1 = {da, ba, ca1} b1 = {da, ba, ca1} a1 = {da, ba, ca1} cwd t rtr t q (b1) spt04221 q ( wr a1 this rd gets the old data retire is automatic here unless: (1) no colc packet (s = 0) or (2) colc packet is rd to device da ctm/cfm col0 col4... row0 row2... wr a1 t2 t0 t1 t3 t4 retire (a1) msk (a1) col0 col4... row0 row2... ctm/cfm t7 t5 t6 t8 t9 t12 t10 t11 t13 t14 t0 t1 this rd gets the new data cac rd b1 msk (a1) retire (a1) t rd c1 cac t t4 t2 t3 t5 t6 t9 t7 t8 t10 t11 t14 t13 t12 t15 t16 t19 t18 t17 t20 t21 t23 t22
direct rdram 128/144-mbit (256k 16/18 32s) data book 34 2.00 figure 18 (left) shows the result of performing a rd command to the same device in the same colc packet slot that would normally be used for the retire operation. the read may be to any bank and column address; all that matters is that it is to the same device as the wr command. the retire operation and msk(a1) will be delayed by a time t packet as a result. if the rd command used the same bank and column address as the wr command, the old data from the sense amp would be returned. if many rd commands to the same device were issued instead of the single one that is shown, then the retire operation would be held off an arbitrarily long time. however, once a rd to another device or a wr or nocop to any device is issued, the retire will take place. figure 18 (right) illustrates a situation in which the controller wants to issue a wr-wr-rd colc packet sequence, with all commands addressed to the same device, but addressed to any combination of banks and columns. the rd will prevent a retire of the first wr from automatically happening. but the first dualoct d(a1) in the write buffer will be overwritten by the second wr dualoct d(b1) if the rd command is issued in the third colc packet. therefore, it is required in this situation that the controller issue a nocop command in the third colc packet, delaying the rd command by a time of t packet . this situation is explicitly shown in table 13 for the cases in which t ccdelay is equal to t rtr . figure 18 retire held off by read (left) and controller forces wwr gap (right) figure 19 shows a possible result when a retire is held off for a long time (an extended version of figure 18 -left). after a wr command, a series of six rd commands are issued to the same device (but to any combination of bank and column addresses). in the meantime, the bank ba to which the wr command was originally directed is precharged, and a different row rc is activated. when the retire is automatically performed, it is made to this new row, since the write buffer only contains the bank and column address, not the row address. the controller can insure that this doesnt happen by never precharging a bank with an unretired write buffer. note that in a system with more than one rdram, there will never be more than two rdrams with unretired write buffers. this is because dqb8...0 dqa8...0 t transaction a: wr transaction b: rd dqa8...0 dqb8...0 a1 = {da, ba, ca1} b1 = {da, bb, cb1} packet rtr cwd t + t d (a1) q c1 = {da, bc, cc1} b1 = {da, bb, cb1} a1 = {da, ba, ca1} t cwd transaction c: rd transaction b: wr transaction a: wr t d (a1) rtr d (b1) spa04222 row2... ctm/cfm col4... row0 col0 t5 the retire operation for a write can be held off by a read to the same device ctm/cfm col0 row2... row0 col4... wr a1 t0 t1 t2 t4 t3 cac retire (a1) rd b1 msk (a1) t t15 t10 t6 t7 t9 t8 t11 t12 t14 t13 t20 t16 t17 t19 t18 the controller must insert a nocop to retire (a1) to make room for the data (b1) in the write buffer wr a1 wr b1 retire (a1) msk (a1) rd c1 t0 t1 t3 t2 t4 t5 t6 t9 t8 t7 t10 t11 t14 t13 t12 t15 t16 cac t t19 t18 t17 t20
data book 35 2.00 direct rdram 128/144-mbit (256k 16/18 32s) a wr command issued to one device automatically retires the write buffers of all other devices written a time t rtr before or earlier. figure 19 retire held off by reads to same device, write buffer retired to new row cwd t cac t a0 = {da, ba, ra} b4 = {da, bb, cb4} b1 = {da, bb, cb1} dqa8...0 dqb8...0 transaction a: wr transaction c: wr transaction b: rd c0 = {da, ba, rc} b5 = {da, bb, cb5} b2 = {da, bb, cb2} a1 = {da, ba, ca1} d (a1) this sequence is hazardous q (b2) b6 = {da, bb, cb6} b3 = {da, bb, cb3} q (b1) a2 = {da, ba} with caution and must be used warning q (b3) q (b4) spt04223 q (b5) t24 act a0 row2... row0 col4...col0 ctm/cfm t2 t0 t1 t3 t4 t wr a1 rd b1 rd b2 ras t rc t14 t7 t5 t6 t8 t9 t10 t11 t13 t12 t19 t15 t16 t18 t17 t20 t21 t23 t22 msk (a1) retire (a1) write data in the new row the retire operation puts the act c0 rd b5 rtr t rcd t rd b3 rd b4 prer a2 rp t rd b6 t34 t29 t25 t26 t27 t28 t30 t31 t32 t33 t39 t36 t35 t37 t38 t41 t40 t42 t43 t46 t45 t44 t47
direct rdram 128/144-mbit (256k 16/18 32s) data book 36 2.00 interleaved write - example figure 20 shows an example of an interleaved write transaction. transactions similar to the one presented in figure 16 are directed to non-adjacent banks of a single rdram. this allows a new transaction to be issued once every t rr interval rather than once every t rc interval (four times more often). the dq data pin efficiency is 100% with this sequence. with two dualocts of data written per transaction, the col, dqa, and dqb pins are fully utilized. banks are precharged using the wra autoprecharge option rather than the prer command in an rowr packet on the row pins. in this example, the first transaction is directed to device da and bank ba. the next three transactions are directed to the same device da, but need to use different, non-adjacent banks bb, bc, bd so there is no bank conflict. the fifth transaction could be redirected back to bank ba without interference, since the first transaction would have completed by then ( t rc has elapsed). each transaction may use any value of row address (ra, rb, ) and column address (ca1, ca2, cb1, cb2, ). figure 20 interleaved write transaction with two dualoct data length y1 = {da, ba+4, cy1} z1 = {da, ba+6, cz1} a1 = {da, ba, ca1} b1 = {da, ba+2, cb1} c1 = {da, ba+4, cc1} d1 = {da, ba+6, cd1} e1 = {da, ba, ce1} f1 = {da, ba+2, cf1} transaction y: wr transaction z: wr transaction a: wr transaction b: wr transaction c: wr transaction d: wr transaction e: wr transaction f: wr y0 = {da, ba+4, ry} z0 = {da, ba+6, rz} a0 = {da, ba, ra} b0 = {da, ba+2, rb} c0 = {da, ba+4, rc} d0 = {da, ba+6, rd} e0 = {da, ba, re} f0 = {da, ba+2, rf} spa04224 f3 = {da, ba+2} e3 = {da, ba} d3 = {da, ba+6} c3 = {da, ba+4} b3 = {da, ba+2} z3 = {da, ba+6} y3 = {da, ba+4} a3 = {da, ba} f2 = {da, ba+2, cf2} e2 = {da, ba, ce2} d2 = {da, ba+6, cd2} c2 = {da, ba+4, cc2} b2 = {da, ba+2, cb2} z2 = {da, ba+6, cz2} y2 = {da, ba+4, cy2} a2 = {da, ba, ca2} t24 d (a1) act a0 row0 row2... col4...col0 dqb8...0 dqa8...0 d (y1) wr z1 ctm/cfm t2 t1 t0 t3 t4 msk (y2) d (y2) rcd t wra z2 wr a1 act b0 d (z2) d (z1) t cwd act c0 t7 t6 t5 t8 t9 t12 t11 t10 t13 t14 t17 t15 t16 t18 t19 rc t t22 t20 t21 t23 t44 d (c2) transaction e can use the same bank as transaction a d (a2) d (b1) act d0 t rr d (c1) d (b2) act e0 act f0 t34 t29 t27 t25 t26 t28 t32 t30 t31 t33 t39 t37 t35 t36 t38 t40 t41 t43 t42 t45 t46 t47 d (x2) d (d1) msk (y1) msk (z1) wr a2 msk (z2) wr b1 msk (a1) wr b2 msk (a2) wr c1 msk (b1) wr c2 msk (b2) wr d1 msk (c1) wr d2 msk (c2) wr e1 msk (d1) wr e2 msk (d2)
data book 37 2.00 direct rdram 128/144-mbit (256k 16/18 32s) interleaved read - example figure 21 shows an example of interleaved read transactions. transactions similar to the one presented in figure 15 are directed to non-adjacent banks of a single rdram. the address sequence is identical to the one used in the previous write example. the dq data pins efficiency is also 100%. the only difference with the write example (aside from the use of the rd command rather than the wr command) is the use of the prex command in a colx packet to precharge the banks rather than the rda command. this is done because the prex is available for a read transaction but is not available for a masked write transaction. interleaved rrww - example figure 22 shows a steady-state sequence of 2-dualoct rd/rd/wr/wr transactions directed to non-adjacent banks of a single rdram. this is similar to the interleaved write and read examples in figure 20 and figure 21 except that bubble cycles need to be inserted by the controller at read/write boundaries. the dq data pin efficiency for the example in figure 22 is 32/42 or 76%. if there were more rdrams on the channel, the dq pin efficiency would approach 32/34 or 94% for the two-dualoct rrww sequence (this case is not shown). in figure 22 , the first bubble type t cbub1 is inserted by the controller between a rd and wr command on the col pins. this bubble accounts for the round-trip propagation delay that is seen by read data, and is explained in detail in figure 4 . this bubble appears on the dqa and dqb pins as t dbub1 between a write data dualoct d and read data dualoct q. this bubble also appears on the row pins as t rbub1 . figure 21 interleaved read transaction with two dualoct data length y1 = {da, ba+4, cy1} z1 = {da, ba+6, cz1} a1 = {da, ba, ca1} b1 = {da, ba+2, cb1} c1 = {da, ba+4, cc1} d1 = {da, ba+6, cd1} e1 = {da, ba, ce1} f1 = {da, ba+2, cf1} transaction y: rd transaction z: rd transaction a: rd transaction b: rd transaction c: rd transaction d: rd transaction e: rd transaction f: rd y0 = {da, ba+4, ry} z0 = {da, ba+6, rz} a0 = {da, ba, ra} b0 = {da, ba+2, rb} c0 = {da, ba+4, rc} d0 = {da, ba+6, rd} e0 = {da, ba, re} f0 = {da, ba+2, rf} spt04225 f3 = {da, ba+2} e3 = {da, ba} d3 = {da, ba+6} c3 = {da, ba+4} b3 = {da, ba+2} z3 = {da, ba+6} y3 = {da, ba+4} a3 = {da, ba} f2 = {da, ba+2, cf2} e2 = {da, ba, ce2} d2 = {da, ba+6, cd2} c2 = {da, ba+4, cc2} b2 = {da, ba+2, cb2} z2 = {da, ba+6, cz2} y2 = {da, ba+4, cy2} a2 = {da, ba, ca2} t24 rd b2 q (a1) prex a3 act a0 row0 row2... col4...col0 dqb8...0 dqa8...0 q (x2) rd z1 ctm/cfm t2 t1 t0 t3 t4 prex z3 prex y3 q (y1) q (y2) rcd t rd z2 rd a1 act b0 q (z2) q (z1) t cac act c0 rd b1 rd a2 t7 t6 t5 t8 t9 t12 t11 t10 t13 t14 t17 t15 t16 t18 t19 rc t t22 t20 t21 t23 t44 rd e1 q (c2) transaction e can use the same bank as transaction a prex b3 q (a2) q (b1) rd c1 act d0 t rd c2 rr prex c3 q (c1) q (b2) rd d2 rd d1 act e0 act f0 t34 t29 t27 t25 t26 t28 t32 t30 t31 t33 t39 t37 t35 t36 t38 t40 t41 t43 t42 prex q (d1) rd e2 t45 t46 t47
direct rdram 128/144-mbit (256k 16/18 32s) data book 38 2.00 the second bubble type t cbub2 is inserted (as a nocop command) by the controller between a wr and rd command on the col pins when there is a wr-wr-rd sequence to the same device. this bubble enables write data to be retired from the write buffer without being lost, and is explained in detail in figure 18 . there would be no bubble if address c0 and address d0 were directed to different devices. this bubble appears on the dqa and dqb pins as t dbub2 between a write data dualoct d and read data dualoct q. this bubble also appears on the row pins as t rbub2 . figure 22 interleaved rrww sequence with two dualoct data length y1 = {da, ba+4, cy1} z1 = {da, ba+6, cz1} a1 = {da, ba, ca1} b1 = {da, ba+2, cb1} c1 = {da, ba+4, cc1} d1 = {da, ba+6, cd1} e1 = {da, ba, ce1} f1 = {da, ba+2, cf1} transaction z: rd transaction a: rd transaction d: rd transaction e: rd transaction y: wr transaction b: wr transaction c: wr transaction f: wr y0 = {da, ba+4, ry} z0 = {da, ba+6, rz} a0 = {da, ba, ra} b0 = {da, ba+2, rb} c0 = {da, ba+4, rc} d0 = {da, ba+6, rd} e0 = {da, ba, re} f0 = {da, ba+2, rf} spt04226 f3 = {da, ba+2} e3 = {da, ba} d3 = {da, ba+6} c3 = {da, ba+4} b3 = {da, ba+2} z3 = {da, ba+6} y3 = {da, ba+4} a3 = {da, ba} e2 = {da, ba, ce2} a2 = {da, ba, ca2} f2 = {da, ba+2, cf2} d2 = {da, ba+6, cd2} c2 = {da, ba+4, cc2} b2 = {da, ba+2, cb2} z2 = {da, ba+6, cz2} y2 = {da, ba+4, cy2} wra b2 prex a3 t5 act a0 row0 dqb8...0 dqa8...0 col4...col0 t d (y2) dbub1 rd z1 cbub2 t row2... ctm/cfm t0 t1 t2 t3 t4 act b0 act c0 rd a2 prex z3 q (z1) dbub2 t rd a1 rd z2 q (z2) q (a1) cbub1 wr b1 t rbub2 t t10 t6 t7 t8 t9 t12 t11 t13 t14 t17 t16 t15 t18 t19 t22 t21 t20 t23 t24 transaction e can use the same bank as transaction a rd d0 act e0 act d0 d (b2) d (b1) q (a2) wr c1 msk (b1) msk (b2) wra c2 d (c1) d (c2) dbub1 t nocop msk (c2) cbub2 msk (c1) nocop t rbub2 t t27 t26 t25 t28 t29 t32 t31 t30 t33 t34 t37 t36 t35 t38 t39 t42 t40 t41 t43 t44 t47 t45 t46 msk (y2)
data book 39 2.00 direct rdram 128/144-mbit (256k 16/18 32s) control register transactions the rdram has two cmos input pins sck and cmd and two cmos input/output pins sio0 and sio1. these provide serial access to a set of control registers in the rdram. these control registers provide configuration information to the controller during the initialization process. they also allow an application to select the appropriate operating mode of the rdram. sck (serial clock) and cmd (command) are driven by the controller to all rdrams in parallel. sio0 and sio1 are connected (in a daisy chain fashion) from one rdram to the next. in normal operation, the data on sio0 is repeated on sio1, which connects to sio0 of the next rdram (the data is repeated from sio1 to sio0 for a read data packet). the controller connects to sio0 of the first rdram. figure 23 serial write (swr) transaction to control register write and read transactions are each composed of four packets, as shown in figure 23 and figure 24 . each packet consists of 16 bits, as summarized in figure 15 and figure 16 . the packet bits are sampled on the falling edge of sck. a transaction begins with a srq (serial request) packet. this packet is framed with a 11110000 pattern on the cmd input (note that the cmd bits are sampled on both the falling edge and the rising edge of sck). the srq packet contains the sop3sop0 (serial opcode) field, which selects the transaction type. the sdev5sdev0 (serial device address) selects one of the 32 rdrams. if sbc (serial broadcast) is set, then all rdrams are selected. the sa (serial address) packet contains a 12 bit address for selecting a control register. a write transaction has a sd (serial data) packet next. this contains 16 bits of data that is written into the selected control register. a sint (serial interval) packet is last, providing some delay for any side-effects to take place. a read transaction has a sint packet, then a sd packet. this provides delay for the selected rdram to access the control register. the sd read data packet travels in the opposite direction (towards the controller) from the other packet types. the sck cycle time will accommodate the total delay. spt04227 t36 sio1 1111 sio0 cmd 0000 sck t4 each packet is repeated srq - swr command from sio0 to sio1 00000000...00000000 srq-swr command sa 00000000...00000000 sa t20 sd 00000000...00000000 sd sint sint 00000000...00000000 t52 1 1 0 0 1 1111 0 0 t68 1 next transaction
direct rdram 128/144-mbit (256k 16/18 32s) data book 40 2.00 figure 24 serial read (srd) transaction control register srq - srd command sio1 first 3 packets are repeated from sio0 to sio1 sa non-addressed rdrams pass 0/sd15...sd0/0 from sio1 to sio0 sint 0 sd spt04228 1 0 0 0 addressed rdram drives 0/sd15...sd0/0 on sio0 00000000...00000000 srq-srd command 1111 sio0 cmd 0000 sck t4 t20 00000000...00000000 sa t36 next transaction t52 00000000...00000000 sint 0 sd 0 on sio0 00000000...00000000 controller drives 1 0 1 0 0 t68 1 1111
data book 41 2.00 direct rdram 128/144-mbit (256k 16/18 32s) control register packets figure 25 setr, clrr, setf transaction table 15 summarizes the formats of the four packet types for control register transactions. table 16 summarizes the fields that are used within the packets. figure 25 shows the transaction format for the setr, clrr, and setf commands. these transactions consist of a single srq packet, rather than four packets like the swr and srd commands. the same framing sequence on the cmd input is used, however. these commands are used during initialization prior to any control register read or write transactions. table 15 control register packet formats sck cycle sio0 or sio1 for srq sio0 or sio1 for sa sio0 or sio1 for sint sio0 or sio1 for sd sck cycle sio0 or sio1 for srq sio0 or sio1 for sa sio0 or sio1 for sint sio0 or sio1 for sd 0 rsrv rsrv 0 sd15 8 sop1 sa7 0 sd7 1 rsrv rsrv 0 sd14 9 sop0 sa6 0 sd6 2 rsrv rsrv 0 sd13 10 sbc sa5 0 sd5 3 rsrv rsrv 0 sd12 11 sdev4 sa4 0 sd4 4 rsrv sa11 0 sd11 12 sdev3 sa3 0 sd3 5 sdev5 sa10 0 sd10 13 sdev2 sa2 0 sd2 6 sop3 sa9 0 sd9 14 sdev1 sa1 0 sd1 7 sop2 sa8 0 sd8 15 sdev0 sa0 0 sd0 spt04229 the packet is repeated from sio0 to sio1 srq packet - setr/clrr/setf sio1 1 0 0 srq packet-setr/clrr/setf 1111 sio0 cmd 0000 sck t4 00000000...00000000 1 1 0 0 t20 1
direct rdram 128/144-mbit (256k 16/18 32s) data book 42 2.00 table 16 field description for control register packets field description rsrv reserved. should be driven as 0 by controller. sop3 sop0 0000 - srd. serial read of control register {sa11 sa0} of rdram {sdev5 sdev0}. 0001 - swr. serial write of control register {sa11 sa0} of rdram {sdev5 sdev0}. 0010 - setr. set reset bit, all control registers assume their reset values. 1) 16 t scycle delay until clrr command. 0100 - setf. set fast (normal) clock mode. 4 t scycle delay until next command. 1011 - clrr. clear reset bit, all control registers retain their reset values. 1) 4 t scycle delay until next command. 1111 - nop. no serial operation. 0011, 0101-1010, 1100-1110 - rsrv. reserved encodings. sdev5 sdev0 serial device. compared to sdevid5sdevid0 field of init control register field to select the rdram to which the transaction is directed. sbc serial broadcast. when set, rdrams ignore {sdev5 sdev0} for rdram selection. sa11sa0 serial address. selects which control register of the selected rdram is read or written. sd15sd0 serial data. the 16 bits of data written to or read from the selected control register of the selected rdram. 1) the setr and clrr commands must always be applied in two successive transactions to rdrams; i.e. they may not be used in isolation. this is called setr/clrr reset.
data book 43 2.00 direct rdram 128/144-mbit (256k 16/18 32s) initialization figure 26 sio reset sequence initialization refers to the process that a controller must go through after power is applied to the system or the system is reset. the controller prepares the rdram sub-system for normal channel operation by (primarily) using a sequence of control register transactions on the serial cmos pins. the following steps outline the sequence seen by the various memory subsystem components (including the rdram components) during initialization. this sequence is available in the form of reference code. contact rambus inc. for more information. 1. start clocks C this step calculates the proper clock frequencies for pclk (controller logic), synclk (rac block), refclk (drcg component), ctm (rdram component), and sck (sio block). 2. rac initialization C this step causes the init block to generate a sequence of pulses which resets the rac, performs rac maintenance operations, and measures timing intervals in order to ensure clock stability. 3. rdram initialization C this stage performs most of the steps needed to initialize the rdrams. the rest are performed in stages 5.0, 6.0, and 7.0. all of the steps in 3.0 are carried out through the sio block interface. 3.1./3.2. sio reset C this reset operation is performed before any sio control register read or write transactions. it clears six registers (test34, cca, ccb, skip, test78, and test79) and places the init register into a special state (all bits cleared except skp and sdevid fields are set to ones). 3.3. write test77 register C the test77 register must be explicitly written with zeros before any other registers are read or written. 3.4. write tcycle register C the tcycle register is written with the cycle time t cycle of the ctm clock (for channel and rdrams) in units of 64ps. the t cycle value is determined in stage 1.0. 3.5. write sdevid register C the sdevid (serial device identification) register of each rdram is written with a unique address value so that directed sio read and write transactions can be performed. this address value increases from 0 to 31 according to the distance an rdram is from the asic component on the sio bus (the closest rdram is address 0). spt04230 from sio0 to sio1 the packet is repeated sio1 0000000000000000 1 0 0 00001100 sio0 cmd sck t0 00000000...00000000 0000000000000000 1 1 0 0 t16 1
direct rdram 128/144-mbit (256k 16/18 32s) data book 44 2.00 3.6. write devid register C the devid (device identification) register of each rdram is written with a unique address value so that directed memory read and write transactions can be performed. this address value increases from 0 to 31. the devid value is not necessarily the same as the sdevid value. rdrams are sorted into regions of the same core configuration (number of bank, row, and column address bits and core type). 3.7. write pdnx,pdnxa registers C the pdnx and pdnxa registers are written with values that are used to measure the timing intervals connected with an exit from the pdn (powerdown) power state. 3.8. write napx register C the napx register is written with values that are used to measure the timing intervals connected with an exit from the nap power state. 3.9. write tparm register C the tparm register is written with values which determine the time interval between a col packet with a memory read command and the q packet with the read data on the channel. the values written set each rdram to the minimum value permitted for the system. this will be adjusted later in stage 6.0. 3.10. write tcdly1 register C the tcdly1 register is written with values which determine the time interval between a col packet with a memory read command and the q packet with the read data on the channel. the values written set each rdram to the minimum value permitted for the system. this will be adjusted later in stage 6.0. 3.11. write tfrm register C the tfrm register is written with a value that is related to the t rcd parameter for the system. the t rcd parameter is the time interval between a row packet with an activate command and the col packet with a read or write command. 3.12. 3.12 setr/clrr C each rdram is given a setr command and a clrr command through the sio block. this sequence performs a second reset operation on the rdrams. 3.13. write cca and ccb registers - these registers are written with a value halfway between their minimum and maximum values. this shortens the time needed for the rdrams to reach their steady-state current control values in stage 5.0. 3.14. powerdown exit C the rdrams are in the pdn power state at this point. a broadcast pdnexit command is performed by the sio block to place the rdrams in the rlx (relax) power state in which they are ready to receive row packets. 3.15. setf - each rdram is given a setf command through the sio block. one of the operations performed by this step is to generate a value for the as (autoskip) bit in the skip register and fix the rdram to a particular read domain. 4. controller configuration C this stage initializes the controller block. each step of this stage will set a field of the configrmc[63:0] bus to the appropriate value. other controller implementations will have similar initialization requirements, and this stage may be used as a guide. 4.1. initial read data offset C the configrmc bus is written with a value which determines the time interval between a col packet with a memory read command and the q packet with the read data on the channel. the value written sets rmc.d1 to the minimum value permitted for the system. this will be adjusted later in stage 6.0. 4.2. configure row/column timing C this step determines the values of the t ras,min , t rp,min , t rc,min , t rcd,min , t rr,min , and t pp,min rdram timing parameters that are present in the system. the configrmc bus is written with values that will be compatible with all rdram devices that are present. 4.3. set refresh interval C this step determines the values of the t ref,max rdram timing parameter that are present in the system. the configrmc bus is written with a value that will be compatible with all rdram devices that are present.
data book 45 2.00 direct rdram 128/144-mbit (256k 16/18 32s) 4.4. set current control interval C this step determines the values of the t cctrl,max rdram timing parameter that are present in the system. the configrmc bus is written with a value that will be compatible with all rdram devices that are present. 4.5. set slew rate control interval C this step determines the values of the t temp,max rdram timing parameter that are present in the system. the configrmc bus is written with a value that will be compatible with all rdram devices that are present. 4.6. set bank/row/col address bits C this step determines the number of rdram bank, row, and column address bits that are present in the system. it also determines the rdram core types (independent, doubled, or split) that are present. the configrmc bus is written with a value that will be compatible with all rdram devices that are present. 5. rdram current control C this step causes the init block to generate a sequence of pulses which performs rdram maintenance operations. 6. rdram core, read domain initialization C this stage completes the rdram initialization 6.1. rdram core initialization C a sequence of 192 memory refresh transactions is performed in order to place the cores of all rdrams into the proper operating state. 6.2. rdram read domain initialization - a memory write and memory read transaction is performed to each rdram to determine which read domain each rdram occupies. the programmed delay of each rdram is then adjusted so the total rdram read delay (propagation delay plus programmed delay) is constant. the tparm and tcdly1 registers of each rdram are rewritten with the appropriate read delay values. the configrmc bus is also rewritten with an updated value. 7. other rdram register fields C this stage rewrites the init register with the final values of the lsr, nsr, and psr fields. in essence, the controller must read all the read-only configuration registers of all rdrams (or it must read the spd device present on each rimm), it must process this information, and then it must write all the read-write registers to place the rdrams into the proper operating mode. initialization note [1]: during the initialization process, it is necessary for the controller to perform 128 current control operations (3xcal, 1xcal/sam) and one temperature calibrate operation (tcen/tcal) after reset or after powerdown (pdn) exit. initialization note [2]: there are two classes of 64/72mbit rdram. they are distinguished by the s28ieco bit in the spd. the behavior of the rdram at initialization is slightly different for the two types: s28ieco = 0: upon powerup the device enters attn state. the serial operations setr, clrr, and setf are performed without requiring a sdevid match of the sbc bit (broadcast) to be set. s28ieco = 1: upon powerup the device enters pdn state. the serial operations setr, clrr, and setf require a sdevid match. see the document detailing the reference initialization procedure for more information on how to handle this in a system. initialization note [3]: after the step of equalizing the total read delay of each rdram has been completed (i.e. after the tcdly0 and tcdly1 fields have been written for the final time), a single final memory read
direct rdram 128/144-mbit (256k 16/18 32s) data book 46 2.00 transaction should be made to each rdram in order to ensure that the output pipeline stages have been cleared. initialization note [4]: the setf command (in the serial srq packet) should only be issued once during the initialization process, as should the setr and clrr commands. initialization note [5]: the clrr command (in the serial srq packet) leaves some of the contents of the memory core in an indeterminate state. control register summary table 17 summarizes the rdram control registers. detail is provided for each control register in figure 27 through figure 43 . read-only bits which are shaded gray are unused and return zero. read-write bits which are shaded gray are reserved and should always be written with zero. the rimm spd application note (dl-0054) describes additional read-only configuration registers which are present on direct rimms. the state of the register fields are potentially affected by the io reset operation or the setr/clrr operation. this is indicated in the text accompanying each register diagram. table 17 control register summary sa11sa0 register field read-write/ read-only description 021 16 init sdevid read-write, 6 bits serial device id. device address for control register read/write. psx read-write, 1 bit power select exit. pdn/nap exit with device addr on dqa5 0. srp read-write, 1 bit sio repeater. used to initialize rdram. nsr read-write, 1 bit nap self-refresh. enables self-refresh in nap mode. psr read-write, 1 bit pdn self-refresh. enables self-refresh in pdn mode. lsr read-write, 1 bit low power self-refresh. enables low power self-refresh. ten read-write, 1 bit temperature sensing enable. tsq read-write, 1 bit temperature sensing output. dis read-write, 1 bit rdram disable. 022 16 test34 test34 read-write, 16 bits test register. do not read or write after sio reset. 023 16 cnfga refbit read-only, 3 bit refresh bank bits. used for multi-bank refresh. dbl read-only, 1 bit double. specifies doubled-bank architecture mver read-only, 6 bit manufacturer version. manufacturer identification number. pver read-only, 6 bit protocol version. specifies version of direct protocol supported.
data book 47 2.00 direct rdram 128/144-mbit (256k 16/18 32s) 024 16 cnfgb byt read-only, 1 bit byte. specifies an 8-bit or 9-bit byte size. devtyp read-only, 3 bit device type. device can be rdram or some other device category. spt read-only, 1 bit split-core. each core half is an individual dependent core. corg read-only, 6 bit core organization. bank, row, column address field sizes. sver read-only, 6 bit stepping version. mask version number. 040 16 devid devid read-write, 5 bits device id. device address for memory read/write. 041 16 refb refb read-write, 4 bits refresh bank. next bank to be refreshed by self-refresh. 042 16 refr refr read-write, 9 bits refresh row. next row to be refreshed by refa, self- refresh. 043 16 cca cca read-write, 7 bits current control a. controls i ol output current for dqa. asyma read-write, 2 bits asymmetry control. controls asymmetry of v ol / v oh swing for dqa. 044 16 ccb ccb read-write, 7 bits current control b. controls i ol output current for dqb. asymb read-write, 2 bits asymmetry control. controls asymmetry of v ol / v oh swing for dqb. 045 16 napx napxa read-write, 5 bits nap exit. specifies length of nap exit phase a. napx read-write, 5 bits nap exit. specifies length of nap exit phase a + phase b. dqs read-write, 1 bits dq select. selects cmd framing for nap/pdn exit. 046 16 pdnxa pdnxa read-write, 13 bits pdn exit. specifies length of pdn exit phase a. 047 16 pdnx pdnx read-write, 13 bits pdn exit. specifies length of pdn exit phase a + phase b. 048 16 tparm tcas read-write, 2 bits t cas-c core parameter. determines t offp data sheet parameter. tcls read-write, 2 bits t cls-c core parameter. determines t cac and t offp parameters. tcdly0 read-write, 3 bits t cdly0-c core parameter. programmable delay for read data. 049 16 tfrm tfrm read-write, 4 bits t frm-c core parameter. determines row-col packet framing interval. 04a 16 tcdly1 tcdly1 read-write, 3 bits t cdly1-c core parameter. programmable delay for read data. 04c 16 tcycle tcycle read-write, 14 bits t cycle data sheet parameter. specifies cycle time in 64 ps units. table 17 control register summary (contd) sa11sa0 register field read-write/ read-only description
direct rdram 128/144-mbit (256k 16/18 32s) data book 48 2.00 04b 16 skip as read-only, 1 bit autoskip value established by the setf command. mse read-write, 1 bit manual skip enable. allows the ms value to override the as value. ms read-write, 1 bit manual skip value. 04d 16- test77 test77 read-write, 16 bits test register. write with zero after sio reset. 04e 16- test78 test78 read-write, 16 bits test register. do not read or write after sio reset. 04f 16- test79 test79 read-write, 16 bits test register. do not read or write after sio reset. 080 16 - 0ff 16 reserved reserved vendor-specific vendor-specific test registers. do not read or write after sio reset. table 17 control register summary (contd) sa11sa0 register field read-write/ read-only description
data book 49 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 27 init register 0 15 14131211109876543210 control register: init sde vid 5 dis tsq ten lsr psr nsr srp psx 0 sdevid4...sdevid0 spd04273 address: 021 16 psx - power exit select. pdn and nap are exited with (=0) or without (=1) a device address on the dqa5..0 pins. pdev5 (on dqa5) selectes broadcast (1) or directed (0) exit. for a directed exit, pdev4..0 (on dqa4..0) is compared to devid4..0 to select a device. s rp - sio repeater. controls value on sio; sio1 = sio0 if srp = 1, sio1 = 1 if srp = 0 srp resets to 1. nap self-refresh. nsr = 1 enables self-refresh in nap mode. nsr cant be set while in nap mode. nsr resets to 0. pdn self-refresh. psr=1 enables self-refresh in pdn mode. psr cant be set while in pdn mode. psr resets to 0. low power self-refresh. lsr = 1 enables longer self-refresh interval. the self-refresh supply current is reduced. lsr resets to 0. temperature sensing enable. ten = 1 enables temperature sensing circuitry, permitting the tsq bit to be read to determine if a thermal trip point has been exceeded. ten resets to 0. temperature sensing output. tsq = 1 when a temperature trip point has been exceeded, tsq = 0 when it has not. tsq is available during a current control operation (see figure 51). rdram disable. dis = 1 causes rdram to ignore nap/pdn exit sequence, dis = 0 permits normal operation. this mechanism disables an rdram. dis resets to 0. sdevid5..0 - serial device identification. compared to sdev5..0 serial address field of serial request packet for register read/write transactions. this determines which rdram is selected for the register read or write operation. sdevid resets to 3f 16 . read/write register. reset values are undefined except as affected by sio reset as noted below. setr/clrr reset does not affect this register.
direct rdram 128/144-mbit (256k 16/18 32s) data book 50 2.00 figure 28 cnfga register figure 29 cnfgb register 15 14131211109876543210 control register: cnfga pver5...0 = 000001 mver5...0 = mmmmmm refbit2...0 = 100 dbl 1 address: 023 16 dbl - doubled-bank. dbl = 1 means the device uses a doubled-bank architecture with adjacent-bank dependency. dbl = 0 means no dependency. mver5..0 - manufacturer version. specifies the manufacturer identification number. pver5..0 - protocol version. specifies the direct protocol version used by this device: 0 - compliant with version 0.62. 1 - compliant with version 0.7 through this version. 2 to 63 - reserved. read-only register. refbit2..0 - refresh bank bits. specifies the number of bank address bits used by refa and refp commands. permits multi-bank refresh in future rdrams. note: in rdrams with protocol version 1 pver[5:0] = 000001, the range of the pdnx field (pdnx[2:0] in the pdnx register) may not be large enough to specify the location of the restricted interval in figure 47. in this case, the effective t s4 parameter must increase and no row or column packets may overlap the restricted interval. see figure 47 and table 19. spd04274 15 14131211109876543210 control register: cnfgb sver5...0 = ssssss corg4...0 = xxxxx devtyp2...0 = 000 spt 1 byt b address: 024 16 devtyp2..0 - device type. devtyp = 000 means that this device is an rdram. byt - byte width. b = 1 means the device reads and writes 9-bit memory bytes. b = 0 means 8 bits. corg4..0 - core organization. this field specifies the number of bank (3, 4, 5, or 6 bits), row (9, 10, 11, or 12 bits), and column (5, 6, or 7 bits) address bits. the encoding of this field will be specified in a later version of this document. sver5..0 - stepping version. specifies the mask version number of this device. spt - split-core. spt = 1 means the core is split, spt = 0 means it is not. read-only register. spd04255
data book 51 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 30 test register figure 31 devid register 11 0 14 0 0 15 0 0 13 12 address: 022 16 control register: test34 0 0 10 9 0 0 0 7 86 3 0 0 0 54 0 0 21 0 0 read/write registers. reset value of test34 is zero ( from sio reset). this register are used for testing purposes. it must not be read or written after sio reset. spd04276 11 0 14 0 0 15 0 0 13 12 address: 040 16 control register: devid 0 0 10 9 0 0 0 7 86 3 0 54 devid4...devid0 210 read/write register. reset value is undefined. device identification register. devid4..devid0 is compared to dr4..dr0, dc4..dc0, and dx4..dx0 fields for all memory read or write transactions. this determines which rdram is selected for the memory read or write transaction. spd04277
direct rdram 128/144-mbit (256k 16/18 32s) data book 52 2.00 figure 32 refb register figure 33 cca register 11 0 14 0 0 15 0 0 13 12 address: 041 16 control register: refb 0 0 10 9 0 0 0 7 86 3 00 5420 read/write register. reset value is zero (from setr/clrr). refresh bank register. refb4..refb0 is the bank that will be refreshed next during self-refresh. refb4..0 is incremented after each self-refresh activate and precharge operation pair. refb4...refb0 1 spd04256 11 0 14 0 0 15 0 0 13 12 address: 043 16 control register: cca 0 0 10 9 asyma 0 0 7 86 3 5420 read/write register. reset value is zero (setr/clrr or sio reset). cca6...cca0 - current control a. controls the i ol output current for the dqa8..dqa0 pins. asymb0 control the asymmetry of the v ol / v oh voltage swing about the v ref reference voltage for the dqa8...0 pins. cca6...cca0 1 spd04279
data book 53 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 34 refr register figure 35 ccb register 11 0 14 0 0 15 0 0 13 12 address: 042 16 control register: refr 0 0 10 9 7 86 3 5420 read/write register. reset value is zero (from setr/clrr). refresh row register. refr8...refr0 is the row that will be refreshed next by the refa command or by self-refresh. refr8...0 is incremented when br4...0 = 1111 for the refa command. refr8...0 is incremented when refb4...0 = 1111 for self-refresh. refr8...refr0 1 spd04257 read/write register. reset value is zero (setr/clrr or sio reset). ccb6...ccb0 - current control b. controls the i ol output current for the dqb8...dqb0 pins. asymb0 control the asymmetry of the v ol / v oh voltage swing about the v ref reference voltage for the dqb8...0 pins. 11 0 14 0 0 15 0 0 13 12 address: 044 16 control register: ccb 0 0 10 9 asymb 0 0 7 86 3 5420 ccb6...ccb0 1 spd04281
direct rdram 128/144-mbit (256k 16/18 32s) data book 54 2.00 figure 36 napx register figure 37 pdnxa register 15 14131211109876543210 control register: napx napx4..0 napxa4..0 address: 045 16 napxa4...0 - nap exit phase a. this field speci- fies the number of sck cycles during the first phase for exiting nap mode. it must satisfy: napxa * t scycle 3 t napxa,max do not set this field to zero. napx4...0 - nap exit phase a plus b. this field specifies the number of sck cycles during the first plus second phases for exiting nap mode. it must satisfy: napx * t scycle 3 napxa * t scycle + t napxb,max do not set this field to zero. dqs - dq select. this field specifies the number of sck cycles (0 => 0.5 cycles, 1 => 1.5 cycles) between the cmd pin framing sequence and the device selection on dq5...0. see figure 48 - this field must be written with a 1 for this rdram. read/write register. reset value is undefined note - t scycle is t cycle1 (sck cycle time). 0 dqs 0000 spd04282 11 14 0 0 15 0 13 12 address: 046 16 control register: pdnxa 10 9 pdnxa12...0 7 86 3 54 210 read/write register. reset value is undefined pdnxa4...0 - pdn exit phase a. this field specifies the number of (64 * sck cycle) units during the first phase for exiting pdn mode. it must satisfy: pdnxa * 64 * t scycle 3 t pdnxa, max do not set this field to zero. note - only pdnxa5...0 are implemented. note - t scycle is t cycle1 (sck cycle time). spd04283
data book 55 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 38 pdnx register figure 39 tparm register 11 14 0 0 15 0 13 12 address: 047 16 control register: pdnx 10 9 pdnx12...0 7 86 3 54 210 read/write register. reset value is undefined pdnx4...0 - pdn exit phase a plus b. this field specifies the number of (256 * sck cycle) units during the first plus second phases for exiting pdn mode. it should satisfy: pdnx * 256 * t scycle 3 pdnxa * 64 * t scycle + t pdnxb, max if this equation cant be satisfied, then the maximum pdnx value should be written, and the t s4 / t h4 timing window will be modified (seefigure 49). do not set this field to zero. note - only pdnx2...0 are implemented. note - t scycle is t cycle1 (sck cycle time). spd04284 11 0 14 0 0 15 0 0 13 12 address: 048 16 control register: tparm 0 0 10 9 0 0 7 86 3 tcdly0 54 tcls 21 tcas 0 read/write register. reset value is undefined. tcas1..0 - specifies the t cas-c core parameter in t cycle units. this should be 10 (2 * t cycle ). tcls1..0 - specifies the t cls-c core parameter in t cycle units. should be 10 (2 * t cycle ). tcdly0 - specifies the t cdly0-c core parameter in t cycle units. this adds a programmable delay to q (read data) packets, permitting round trip read delay to all devices to be equalized. this field may be written with the values 010 (2 * t cycle ) through 101 (5 * t cycle ). the equations relating the core parameters to the datasheet parameters follow: t cas-c = 2 * t cycle t cls-c = 2 * t cycle t cps-c = 1 * t cycle not programmable t offp = t cps-c + t cas-c + t cls-c - 1 * t cycle = 4 * t cycle t rcd = t rcd-c + 1 * t cycle - t cls-c = t rcd-c - 1 * t cycle t cac = 3 * t cycle + t cls-c + t cdly0-c + t cdly1-c (see table below for programming ranges) tcdly0 tcdly1 010 000 not allowed t cdly0-c t cdly1-c 7 * t cycle 0 * t cycle 2 * t cycle 011 000 8 * t cycle 0 * t cycle 3 * t cycle 011 001 9 * t cycle 1 * t cycle 3 * t cycle 011 010 10 * t cycle 2 * t cycle 3 * t cycle 100 010 11 * t cycle 2 * t cycle 4 * t cycle 101 010 12 * t cycle 8 * t cycle 9 * t cycle 10 * t cycle 11 * t cycle 12 * t cycle 2 * t cycle 5 * t cycle t cas @ t cycle = 3.3 ns t cas @ t cycle = 2,5 ns spd04285
direct rdram 128/144-mbit (256k 16/18 32s) data book 56 2.00 figure 40 tfrm register figure 41 trdly register 11 0 14 0 0 15 0 0 13 12 address: 049 16 control register: tfrm 0 0 10 9 0 0 0 7 86 3 0 0 5420 read/write register. reset value is undefined. tfrm3...0 - specifies the position of the framing point in t cycle units. this value must be greater or equal to the t frm,min parameter. this is the minimum offset between a row packet (which places a device at attn) and the first col packet (directed to that device) which must be framed. this field may be written with the values 0111 (7 * t cycle ) through 1010 (10 * t cycle ). tfrm is usually set to the value which matches the largest t rcd,min parameter (modulo 4 * t cycle ) that is present in an rdram in the memory system. thus, if an rdram with t rcd, min = 11 * t cycle were present, then tfrm would be programmed to 7 * t cycle . tfrm3...0 1 spd04286 11 0 14 0 0 15 0 0 13 12 address: 04a 16 control register: tcdly1 0 0 10 9 0 0 0 7 86 3 0 00 5420 read/write register. reset value is undefined. tcdly1 - specifies the value of the t cdly1-c core parameter in t cycle units. this adds a programm- able delay to q (read data) packets, permitting round trip read delay to all devices to be equalized. this field may be written with the values 000 (0 * t cycle ) through 010 (2 * t cycle ). refer to figure 39 for more details. tcdly1 1 spd04287
data book 57 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 42 skip register figure 43 test registers 11 mse 14 0 0 15 0 as 13 12 address: 04b 16 control register: skip ms 0 10 9 0 0 0 7 86 3 0 0 0 54 0 0 21 0 0 read/write register (except as field). reset value is zero (sio reset). as - autoskip. read-only value determined by autoskip circuit and stored when setf serial command is received by rdram during initial-ization. in figure 58, as = 1 corresponds to the early q(a1) packet and as = 0 to the q(a1) packet one t cycle later for the four uncertain cases. mse - manual skip enable (0 = auto, 1 = manual). ms - manual skip (ms must be 1 when mse = 1).> during initialization, the rdrams at the furthest point in the fifth read domain may have selected the as = 0 value, placing them at the closest point in a sixth read domain. setting the mse/ms fields to 1/1 overrides the autoskip value and returns them to the furthest point of the fifth read domain. spd04288 11 0 14 0 0 15 0 0 13 12 address: 04f 16 control register: test79 address: 04e 16 control register: test78 address: 04d 16 control register: test77 0 0 10 9 0 0 0 7 86 3 0 0 0 54 0 0 21 0 0 read/write registers. reset value of test78, 79 is zero ( sio reset). do not read or write test78, 79 after sio reset. test77 must be written with zero after sio reset. these registers must only be used for testing purposes. spd04289
direct rdram 128/144-mbit (256k 16/18 32s) data book 58 2.00 figure 44 tcycle register power state management table 18 summarizes the power states available to a direct rdram. in general, the lowest power states have the longest operational latencies. for example, the relative power levels of pdn state and stby state have a ratio of about 1:110, and the relative access latencies to get read data have a ratio of about 250:1. pdn state is the lowest power state available. the information in the rdram core is usually maintained with self-refresh; an internal timer automatically refreshes all rows of all banks. pdn has a relatively long exit latency because the tclk/rclk block must resynchronize itself to the external clock signal. nap state is another low-power state in which either self-refresh or refa-refresh are used to maintain the core. see refresh on page 64 for a description of the two refresh mechanisms. nap has a shorter exit latency than pdn because the tclk/rclk block maintains its synchronization state relative to the external clock signal at the time of nap entry. this imposes a limit ( t nlimit ) on how long an rdram may remain in nap state before briefly returning to stby or attn to update this synchronization state. table 18 power state summary power state description blocks consuming power power state description blocks consuming power pdn powerdown state. self-refresh nap nap state. similar to pdn except lower wake-up latency. self-refresh or refa-refresh tclk/rclk-nap stby standby state. ready for row packets. refa-refresh tclk/rclk row demux receiver attn attention state. ready for row and col packets. refa-refresh tclk/rclk row demux receiver col demux receiver attnr attention read state. ready for row and col packets. sending q (read data) packets. refa-refresh tclk/rclk row demux receiver col demux receiver dq mux transmitter core power attnw attention write state. ready for row and col packets. ready for d (write data) packets. refa-refresh tclk/rclk row demux receiver col demux receiver dq demux receiver core power 11 14 0 0 15 13 12 address: 04c 16 control register: tcycle 10 9 tcycle13...tcycle0 7 86 3 54 210 read/write register. reset value is undefined tcycle13...0 - specifies the value of the t cycle datasheet parameter in 64 ps units. for the t cycle, min of 2.5 ns (2500 ps), this field should be written with the value 00027 16 (39 * 64 ps). spd04290
data book 59 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 45 summarizes the transition conditions needed for moving between the various power states. note that nap and pdn have been divided into two substates (nap-a/nap-s and pdn-a/pdn-s) to account for the fact that a nap or pdn exit may be made to either attn or stby states. at initialization, the setr/clrr reset sequence will put the rdram into pdn-s state. the pdn exit sequence involves an optional pdev specification and bits on the cmd and sio in pins. once the rdram is in stby, it will move to the attn/attnr/attnw states when it receives a non-broadcast rowa packet or non-broadcast rowr packet with the attn command. the rdram returns to stby from these three states when it receives a rlx command. alternatively, it may enter nap or pdn state from attn or stby states with a napr or pdnr command in an rowr packet. the pdn or nap exit sequence involves an optional pdev specification and bits on the cmd and sio0 pins. the rdram returns to the attn or stby state it was originally in when it first entered nap or pdn. an rdram may only remain in nap state for a time t nlimit . it must periodically return to attn or stby. the naprc command causes a napdown operation if the rdrams ncbit is set. the ncbit is not directly visible. it is undefined on reset. it is set by a napr command to the rdram, and it is cleared by an act command to the rdram. it permits a controller to manage a set of rdrams in a mixture of power states. stby state is the normal idle state of the rdram. in this state all banks and sense amps have usually been left precharged and rowa and rowr packets on the row pins are being monitored. when a non-broadcast rowa packet or non-broadcast rowr packet (with the attn command) packet addressed to the rdram is seen, the rdram enters attn state (see the right side of figure 46 ). this requires a time t sa during which the rdram activates the specified row of the specified bank. a time tfrm t cycle after the row packet, the rdram will be able to frame col packets (tfrm is a control register field - see figure 40 ). once in attn state, the rdram will automatically transition to the attnw and attnr states as it receives wr and rd commands.
direct rdram 128/144-mbit (256k 16/18 32s) data book 60 2.00 figure 45 power state transition diagram once the rdram is in attn, attnw, or attnr states, it will remain there until it is explicitly returned to the stby state with a rlx command. a rlx command may be given in an rowr, colc, or colx packet (see the left side of figure 46 ). it is usually given after all banks of the rdram have been precharged; if other banks are still activated, then the rlx command would probably not be given. if a broadcast rowa packet or rowr packet (with the attn command) is received, the rdrams power state doesnt change. if a broadcast rowr packet with rlxr command is received, the rdram goes to stby. spd04231 attnr attn automatic automatic automatic automatic attnw nap-a automatic automatic nap-s nap pdev.cmd x sio0 napr x rlxr napr x rlxr pdev.cmd x sio0 stby pdn-s pdn-a pdn pdnr napr attn pdnr x rlxr pdev.cmd x sio0 pdnr x rlxr pdev.cmd x sio0 rlx setr/clrr nlimit t notation: setr/clrr pdnr napr rlxr rlx sio0 pdev.cmd attn (non-broadcast) with attn command - setr/clrr reset sequence in srq packets - rowa packet (non-broadcast) or rowr packet - rlx command in rowr, colc, colx packets - rlx command in rowr packet - napr command in rowr packet - pdnr command in rowr packet - (pdev = devid) x (cmd = 01) - sio0 input value
data book 61 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 47 shows the nap entry sequence (left). nap state is entered by sending a napr command in a row packet. a time t asn is required to enter nap state (this specification is provided for power calculation purposes). the clock on ctm/cfm must remain stable for a time t cd after the napr command. the rdram may be in attn or stby state when the napr command is issued. when nap state is exited, the rdram will return to the original starting state (attn or stby). if it is in attn state and a rlxr command is specified with napr, then the rdram will return to stby state when nap is exited. figure 47 also shows the pdn entry sequence (right). pdn state is entered by sending a pdnr command in a row packet. a time t asp is required to enter pdn state (this specification is provided for power calculation purposes). the clock on ctm/cfm must remain stable for a time t cd after the pdnr command. the rdram may be in attn or stby state when the pdnr command is issued. when pdn state is exited, the rdram will return to the original starting state (attn or stby). if it is in attn state and a rlxr command is specified with pdnr, then the rdram will return to stby state when pdn is exited. the current- and slew-rate-control levels are re-established. the rdrams write buffer must be retired with the appropriate cop command before nap or pdn are entered. also, all the rdrams banks must be precharged before nap or pdn are entered. the exception to this is if nap is entered with the nsr bit of the init register cleared (disabling self-refresh in nap). the commands for relaxing, retiring, and precharging may be given to the rdram as late as the ropa0, copa0, and xopa0 packets in figure 47 . no broadcast packets nor packets directed to the rdram entering nap or pdn may overlay the quiet window. this window extends for a time t npq after the packet with the napr or pdnr command. figure 48 shows the nap and pdn exit sequences. these sequences are virtually identical; the minor differences will be highlighted in the following description. before nap or pdn exit, the ctm/cfm clock must be stable for a time t ce . then, on a falling and rising edge of sck, if there is a 01 on the cmd input, nap or pdn state will be exited. also, on the falling sck edge the sio0 input must be at a 0 for nap exit and 1 for pdn exit. if the psx bit of the init register is 0, then a device pdev5 0 is specified for nap or pdn exit on the dqa5 0 pins. this value is driven on the rising sck edge 0.5 or 1.5 sck cycles after the original falling edge, depending upon the value of the dqs bit of the napx register. if the psx bit of the init register is 1, then the rdram ignores the pdev5 0 address packet and exits nap or pdn when the wake-up sequence is presented on the cmd wire. the row and col pins must be quiet at a time t s4 / t h4 around the indicated falling sck edge (timed with the pdnx or napx register fields). after that, row and col packets may be directed to the rdram which is now in attn or stby state. figure 49 shows the constraints for entering and exiting nap and pdn states. on the left side, an rdram exits nap state at the end of cycle t 3 . this rdram may not re-enter nap or pdn state for an interval of t nu0 . the rdram enters nap state at the end of cycle t 13 . this rdram may not re-exit nap state for an interval of t nu1 . the equations for these two parameters depend upon a number of factors, and are shown at the bottom of the figure. napx is the value in the napx field in the napx register.
direct rdram 128/144-mbit (256k 16/18 32s) data book 62 2.00 figure 46 stby entry (left) and stby exit (right) figure 47 nap entry (left) and pdn entry (right) on the right side of figure 48 , an rdram exits pdn state at the end of cycle t 3 . this rdram may not re-enter pdn or nap state for an interval of t pu0 . the rdram enters pdn state at the end of cycle t 13 . this rdram may not re-exit pdn state for an interval of t pu1 . the equations for these two parameters depend upon a number of factors, and are shown at the bottom of the figure. pdnx is the value in the pdnx field in the pdnx register. at (tfrm) attn power state t as stby state dqb8...0 dqa8...0 power t cycle spt04232 device (d1!= d0) is okay a col packet to another stby attn sa t or earlier. at (tfrm - 4) * t * cycle rop a0 ctm/cfm row2... row0 col4... col0 dqb8...0 dqa8...0 rlxx rlxc rlxr t0 t3 t1 t2 t4 t5 col4... col0 row2... ctm/cfm row0 t8 t6 t7 t9 t10 t13 t11 t12 t14 t0 t1 t2 a col packet to device d0 (or any other device) is okay a1 = {d1, b1, c1} rowa or rowr/attn rop = non-broadcast no col packets may be placed in the three indicated positions; i.e. at (tfrm - {1, 2, 3}) cop a0 xop a0 tfrm cop a1 xop a1 * t cycle a0 = {d0, b0, r0} t5 t4 t3 t6 t7 t10 t9 t8 t11 t12 t15 t14 t13 t16 cycle t * or later. owerlap the restricted the (eventual) nap / pdn exit will be to the same attn / stby state the rdram was in prior to nap / pdn entry power state a) dqa8...0 dqb8...0 nap a) attn / stby asn t state power dqa8...0 dqb8...0 spt04233 the restricted interval will directed to device d0 after row or col packets attn / stby a) asp t pdn interval be ignored rop a0 cop a0 xop a0 (napr) col0 col4... row0 row2... ctm/cfm t0 t1 t2 t3 restricted rop a1 restricted npq t xop a1 cop a1 t cd col0 col4... row0 ctm/cfm row2... t6 t5 t4 t7 t8 t11 t10 t9 t12 t13 t14 t0 no row or col packets directed to device d0 may overlap the restricted interval. no broadcast row packets may overlap the quiet interval device other than d0 may row or col packets to a a1 = {d1, b1,r1, c1} a0 = {d0, b0, r0, c0} cop a1 xop a1 rop a1 restricted (pdnr) restricted xop a0 cop a0 npq t rop a0 cd t t3 t1 t2 t4 t5 t8 t6 t7 t9 t10 t13 t11 t12
data book 63 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 48 nap and pdn exit t device selection timing slot is selected by dqs field of napx register asserted at nap or pdn entry time the dqs field must be written with "1" for this rdram exit to stby or attn depends upon whether rlxr was d) c) dqs = 0 from sio0 to sio1 nap / pdn the packet is repeated use 0 for nap exit, 1 for pdn exit state power sio1 b) a) 0/1 sio0 cmd sck 0/1 0 ce dqs = 1 bb a a 1 dqs = 0 b spt04234 d stby / attn * + (pdnxa is exiting the nap-a or pdn-a states restricted interval if device pdev no col packets may overlap the effective hold becomes t24 t23 t21 t20 t19 t18 t16 t15 t17 t14 t13 t10 t11 t12 t9 t8 t5 t6 t7 t4 t3 t2 t1 t22 t0 t if psx = 1 in init register, then nap/pdn exit is broadcast (no pdev field). col4...col0 dqa8...0 dqb8...0 row0 ctm/cfm row2... dqs = 1 b, c s3 h3 t s3 t t h3 < (pdnxa if (pdnx tt = h4 h4 * 64 256 * t47 t46 t45 t42 t43 t41 t40 t38 t36 t35 t37 t39 t31 t30 t28 t26 t25 t27 t29 t34 t44 xop cop rop cop restricted pdnxb, max pdnxb, max scycle t * 64 * scycle scycle * t t + t ) t + s4 ) t xop h4 t the restricted interval no row packets may overlap s4 t h4 t (napx scycle t * ) * scycle t ) / (256 pdnx * - (pdnx * 256 * scycle t ) rop restricted ). pdev5...0 pdev5...0 bb
direct rdram 128/144-mbit (256k 16/18 32s) data book 64 2.00 figure 49 nap entry/exit windows (left) and pdn entry/exit windows (right) refresh rdrams, like any other dram technology, use volatile storage cells which must be periodically refreshed. this is accomplished with the refa command. figure 50 shows an example of this. the refa command in the transaction is typically a broadcast command (dr4t and dr4f are both set in the rowr packet), so that in all devices bank number ba is activated with row number refr, where refr is a control register in the rdram. when the command is broadcast and attn is set, the power state of the rdrams (attn or stby) will remain unchanged. the controller increments the bank address ba for the next refa command. when ba is equal to its maximum value, the rdram automatically increments refr for the next refa command. on average, these refa commands are sent once every t ref /2 bbit+rbit (where bbit are the number of bank address bits and rbit are the number of row address bits) so that each row of each bank is refreshed once every t ref interval. the refa command is equivalent to an act command, in terms of the way that it interacts with other packets (see table 12 ). in the example, an act command is sent after t rr to address b0, a different (non-adjacent) bank than the refa command. a second act command can be sent after a time t rc to address c0, the same bank (or an adjacent bank) as the refa command. note that a broadcast refp command is issued a time t ras after the initial refa command in order to precharge the refreshed bank in all rdrams. after a bank is given a refa command, no other core operations (activate or precharge) should be issued to it until it receives a refp. it is also possible to interleave refresh transactions (not shown). in the figure, the act b0 command would be replaced by a refa b0 command. the b0 address would be broadcast to all devices, and pdn exit nap exit + (2 + napx) no entry to nap or pdn if nsr = 1 cmd 5 8 23 nu1 nu1 t t = = nu0 t = cycle cycle cycle * * t t * t - (0.5 0 1 scycle ) if nsr = 0 scycle t * t * nu0 t nu1 no exit t 0 cmd scycle pdnx) no entry to nap or pdn scycle scycle scycle 5 8 23 pu1 pu1 t t = = pu0 t = t * * t * t 0 * if psr = 1 + (2 + 256 - (0.5 t * 1 pu0 t spt04235 pu1 no exit ) if psr = 0 * scycle t t 0 row2... ctm/cfm row0 row2... ctm/cfm sck t2 t0 t1 t3 t4 t6 t5 t7 t18 t13 nap entry t10 t8 t9 t11 t12 napr t14 t15 t17 t16 t19 sck row0 t10 t2 t3 t4 t6 t5 t7 t9 t8 pdn entry napr t13 t11 t12 t14 t15 t17 t16 t18 t19
data book 65 2.00 direct rdram 128/144-mbit (256k 16/18 32s) would be {broadcast,ba+2,refr}. note that the bank address should skip by two to avoid adjacent bank interference. a possible bank incrementing pattern would be: {13, 11, 9, 7, 5, 3, 1, 8, 10, 12, 14, 0, 2, 4, 6, 15, 29, 27, 25, 23, 21, 19, 17, 24, 26, 28, 30, 16, 18, 20, 22, 31}. every time bank 31 is reached, the refa command would automatically increment the refr register. a second refresh mechanism is available for use in pdn and nap power states. this mechanism is called self-refresh mode. when the pdn power state is entered, or when nap power state is entered with the nsr control register bit set, then self-refresh is automatically started for the rdram. self-refresh uses an internal time base reference in the rdram. this causes an activate and precharge to be carried out once in every t ref /2 bbit+rbit interval. the refb and refr control registers are used to keep track of the bank and row being refreshed. before a controller places an rdram into self-refresh mode, it should perform refa/refp refreshes until the bank address is equal to the maximum value. this ensures that no rows are skipped. likewise, when a controller returns an rdram to refa/refp refresh, it should start with the minimum bank address value (zero). figure 50 refa/refp refresh transaction example current and temperature control figure 51 shows an example of a transaction which performs current control calibration. it is necessary to perform this operation once to every rdram in every t cctrl interval in order to keep the i ol output current in its proper range. bbit + rbit /2 a1 = {broadcast, ba} dqa8...0 dqb8...0 transaction a: refa transaction a: refa transaction c: xx transaction b: xx d0 = {broadcast, ba+1, refr} c0 = {dc, ==ba, rc} b0 = {db, /={ba, ba+1, ba-1}, rb} a0 = {broadcast, ba, refr} t ref refr = refr8...refr0 refb = refb3...refb0 bbit = #row address bits bbit = #bank address bits spt04236 t24 refp a1 ctm/cfm col4...col0 row2... row0 refa a0 t2 t0 t1 t3 t4 t rr act b0 t ras t rc t14 t7 t5 t6 t8 t9 t12 t10 t11 t13 t19 t17 t15 t16 t18 t20 t21 t23 t22 t44 refa d0 act c0 rp t t34 t29 t25 t26 t28 t27 t30 t31 t33 t32 t35 t36 t37 t41 t42 t43 t46 t45 t47
direct rdram 128/144-mbit (256k 16/18 32s) data book 66 2.00 this example uses four colx packets with a cal command. these cause the rdram to drive four calibration packets q(a0) a time t cac later. an offset of t rdtocc must be placed between the q(a0) packet and read data q(a1)from the same device. these calibration packets are driven on the dqa4 3 and dqb4 3 wires. the tsq bit of the init register is driven on the dqa5 wire during same interval as the calibration packets. the remaining dqa and dqb wires are not used during these calibration packets. the last colx packet also contains a sam command (concatenated with the cal command). the rdram samples the last calibration packet and adjusts its i ol current value. unlike ref commands, cal and sam commands cannot be broadcast. this is because the calibration packets from different devices would interfere. therefore, a current control transaction must be sent every t cctrl /n, where n is the number of rdrams on the channel. the device field da of the address a0 in the cal/sam command should be incremented after each transaction. figure 23 shows an example of a temperature calibration sequence to the rdram. this sequence is broadcast once every t temp interval to all the rdrams on the channel. the tcen and tcal are rop commands, and cause the slew rate of the output drivers to adjust for temperature drift. during the quiet interval t tcquiet the devices being calibrated cant be read, but they can be written. figure 51 current control cal/sam transaction example hottemp = dqa5 note that dqb3 could be used instead of dqa3. when used for monitoring, it should be enabled with the dqa3 bit (current control one value) in case there is no rdram present: control register; i.e. logic 0 or high voltage means hot temperature. dqa5 of the first calibrate packet has the inverted tsq bit of init readtocc transaction a2: cal/sam transaction a0: cal/sam transaction a1: rd col4...col0 dqb8...0 dqa8...0 q (a1) t cal a0 a1 = {da, bx} a2 = {da, bx} cal/sam a0 q (a0) a0 = {da, bx} cal a0 t cac cal a0 cal a2 dqa3 * q (a1) ccsamtoread t spt04237 t24 packet position or earlier. command must be at this device from an earlier rd read data from the same row0 row2... ctm/cfm t2 t0 t1 t3 t4 t14 device from an earlier rd prior to the q(a0) packet. read data from a different command can be anywhere t5 t6 t8 t7 t9 t10 t11 t13 t12 t t19 t15 t16 t18 t17 t20 t21 t23 t22 packet position or later. device from a later rd command must be at this read data from a different t34 read data from a different command can be anywhere after to the q(a0) packet. cctrl t29 device from a later rd t25 t26 t27 t28 t31 t30 t32 t33 t39 t36 t35 t37 t38 t42 t43 t46 t45 t44 t47
data book 67 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 52 temperature calibration (tcen-tcal) transactions to rdram t being calibrated no read data from devices dqb8...0 dqa8...0 tcal spt04238 t24 tcquiet any row packet may be plased in the gap between the row packets with the tcen and tcal commands. ctm/cfm row2... col4...col0 row0 tcen t2 t0 t1 t3 t4 tcal t tcen t t14 t5 t6 t8 t7 t9 t10 t11 t13 t12 t19 t15 t16 t18 t17 t20 t21 t23 t22 tcen temp t t34 t25 t26 t27 t28 t32 t33 t36 t35 t37 t38 t41 t42 t43 t46 t45 t44 t47
direct rdram 128/144-mbit (256k 16/18 32s) data book 68 2.00 table 19 electrical conditions parameter and conditions symbol limit values unit min. max. junction temperature under bias t j - 100 c supply voltage v dd , v dda 2.50 C 0.13 2.50 + 0.13 v supply voltage droop (dc) during nap interval ( t nlimit ) v dd,n, v dda,n C2.0% supply voltage ripple (ac) during nap interval ( t nlimit ) v dd,n, v dda,n C2.0 2.0 % supply voltage for cmos pins (2.5 v controllers) supply voltage for cmos pins (1.8 v controllers) v cmos 2.50 C 0.13 1.80 C 0.1 2.50 + 0.25 1.80 + 0.2 v v termination voltage v term 1.80 C 0.1 1.80 + 0.1 v reference voltage v ref 1.40 C 0.2 1.40 + 0.2 v rsl data input - low voltage v dil v ref C 0.5 v ref C 0.2 v rsl data input - high voltage v dih v ref + 0.2 v ref + 0.5 v rsl data input swing: v dis = v dih C v dil v dis 0.4 1.0 v rsl data asymmetry: a di = [( v dih C v ref ) + ( v dil C v ref )]/ v dis a di 0 C 20 % rsl clock input - crossing point of true and complement signals v x 1.3 1.8 v rsl clock input - common mode v cm =( v cih + v cil) /2 v cm 1.4 1.7 v rsl clock input swing: v cis = v cih C v cil (ctm, ctmn pins). v cis,ctm 0.35 0.70 v rsl clock input swing: v cis = v cih C v cil (cfm, cfmn pins). v cis,cfm 0.125 0.70 v cmos input low voltage v il,cmos C 0.3 v cmos / 2 C 0.25 v cmos input high voltage v ih,cmos v cmos / 2 + 0.25 v cmos +0.3 v
data book 69 2.00 direct rdram 128/144-mbit (256k 16/18 32s) table 20 timing conditions parameter symbol limit values unit figure min. max. ctm and cfm cycle times (-600) ctm and cfm cycle times (-711) ctm and cfm cycle times (-800) t cycle 3.33 2.80 2.50 3.83 3.83 3.83 ns ns ns figure 53 figure 53 figure 53 ctm and cfm input rise and fall times t cr , t cf 0.2 0.5 ns figure 53 ctm and cfm high and low times t ch , t cl 40% 60% t cycle figure 53 ctm-cfm differential (mse/ms = 0/0) ctm-cfm differential (mse/ms = 1/1) 1) t tr 0.0 0.9 1.0 1.0 t cycle figure 42 figure 53 domain crossing window t dcw C 0.1 0.1 t cycle figure 59 dqa/dqb/row/col input rise/fall times t dr , t df 0.2 0.65 ns figure 54 dqa/dqb/row/col-to-cfm set/hold @ t cycle =3.33ns dqa/dqb/row/col-to-cfm set/hold @ t cycle =2.81ns dqa/dqb/row/col-to-cfm set/hold @ t cycle =2.50ns t s , t h 0.275 2),d 0.240 3),4) 0.200 d C C C ns ns ns figure 54 figure 54 figure 54 sio0, sio1 input rise and fall times t dr1, t df1 C5.0ns figure 56 cmd, sck input rise and fall times t dr2, t df2 C2.0ns figure 56 sck cycle time - serial control register transactions t cycle1 1000 C ns figure 56 sck cycle time - power transitions 10 C ns figure 56 sck high and low times t ch1 , t cl1 4.25 C ns figure 56 cmd setup time to sck rising or falling edge 5) t s1 1.25 C ns figure 56 cmd hold time to sck rising or falling edge c t h1 1Cns figure 56 sio0 setup time to sck falling edge t s2 40Cns figure 56 sio0 hold time to sck falling edge t h2 40Cns figure 56 pdev setup time on dqa5 0 to sck rising edge. t s3 0Cns figure 48 , figure 57 pdev hold time on dqa5 0 to sck rising edge. t h3 5.5 C ns row2 0, col4 0 setup time for quiet window t s4 C 1 C t cycle figure 48 row2 0, col4 0 hold time for quiet window 6) t h4 5C t cycle figure 48
direct rdram 128/144-mbit (256k 16/18 32s) data book 70 2.00 cmos input low voltage - over/undershoot voltage duration is less than or equal to 5 ns v il,cmos C 0.7 v cmos / 2 C 0.4 vC cmos input high voltage - over/undershoot voltage duration is less than or equal to 5 ns v ih,cmos v cmos / 2 + 0.4 v cmos + 0.7 vC quiet on row/col bits during nap/pdn entry t npq 4C t cycle figure 47 offset between read data and cc packets (same device) t readtocc 12 C t cycle figure 51 offset between cc packet and read data (same device) t ccsamtoread 8C t cycle figure 51 ctm/cfm stable before nap/pdn exit t ce 2C t cycle figure 48 ctm/cfm stable after nap/pdn entry t cd 100 C t cycle figure 47 row packet to col packet attn framing delay t frm 7C t cycle figure 46 maximum time in nap mode t nlimit C 10.0 m s figure 45 refresh interval t ref C32ms figure 50 current control interval t cctrl 34 t cycle 100 ms ms/ t cy cle figure 51 temperature control interval t temp C 100 ms figure 23 tce command to tcal command t tcen 150 C t cycle figure 23 tcal command to quiet window t tcal 22 t cycle figure 23 quiet window (no read data) t tcquiet 140 C t cycle figure 23 rdram delay (no rsl operations allowed) t pause C 200.0 m s page 43 1) mse/ms are fields of the skip register. for this combination (skip override) the t dcw parameter range is effectively 0.0 to 0.0. 2) this parameter also applies to a -800 or -711 part when operated with t cycle =3.33ns. 3) this parameter also applies to a -800 part when operated with t cycle =2.81ns. 4) t s,min and t h,min for other t cycle values can be interpolated between or extrapolated from the timings at the 3 specified t cycle values. 5) with v il,cmos =0.5 v cmos C 0.6 v and v ih,cmos =0.5 v cmos +0.6v 6) effective hold becomes t h4 = t h4 + [pdnxa 64 t scycle + t pdnxb,max ] C [pdnx 256 t scycle ] if [pdnx 256 t scycle ] < [pdnxa 64 t scycle + t pdnxb,max ]. see figure 48 . table 20 timing conditions (contd) parameter symbol limit values unit figure min. max.
data book 71 2.00 direct rdram 128/144-mbit (256k 16/18 32s) table 21 electrical characteristics parameter symbol limit values unit min. max. v ref current @ v ref,max i ref C10 10 m a rsl output high current @ (0 v out v dd ) i oh C10 10 m a rsl i ol current @ v ol = 0.9 v, v dd,min , t j,max 1) i all 30.0 90.0 ma rsl i ol current resolution step d i ol C2.0ma dynamic output impedance r out 150 C w cmos input leakage current @ (0 v i,cmos v cmos ) i i,cmos C 10.0 10.0 m a cmos output voltage @ i ol,cmos = 1.0 ma v ol,cmos C0.3v cmos output high voltage @ i oh,cmos = C 0.25 ma v oh,cmos v cmos C0.3 C v 1) this measurement is made in manual current control mode; i.e. with all output device legs sinking current. table 22 timing characteristics parameter symbol limit values unit figure min. max. t q ctm-to-dqa/dqb output time @ t cycle =3.33ns ctm-to-dqa/dqb output time @ t cycle =2.81ns ctm-to-dqa/dqb output time @ t cycle =2.50ns C 0.350 1),3) C 0.300 2),3) C 0.260 3) + 0.350 1),3) + 0.300 2),3) + 0.260 3) ns ns ns figure 55 figure 55 figure 55 t qr , t qf dqa/dqb output rise and fall times 0.2 0.45 ns figure 55 t q1 sck(neg)-to-sio0 delay @ c load,max = 20 pf (sd read data valid). C10ns figure 58 t hr sck(pos)-to-sio0 delay @ c load,max = 20 pf (sd read data hold). 2C ns figure 58 t qr1 , t qf1 sio out rise/fall @ c load,max = 20 pf C 5 ns figure 58 t prop1 sio0-to-sio1 or sio1-to-sio0 delay @ c load,max = 20 pf C10ns figure 58 t napxa nap exit delay - phase a C 50 ns figure 48 t napxb nap exit delay - phase b C 40 ns figure 48 t pdnxa pdn exit delay - phase a C 4 m s figure 48 t pdnxb pdn exit delay - phase b C 9000 t cycle figure 48
direct rdram 128/144-mbit (256k 16/18 32s) data book 72 2.00 rsl - clocking figure 53 is a timing diagram which shows the detailed requirements for the rsl clock signals on the channel. the ctm and ctmn are differential clock inputs used for transmitting information on the dqa and dqb, outputs. most timing is measured relative to the points where they cross. the t cycle parameter is measured from the falling ctm edge to the falling ctm edge. the t cl and t ch parameters are measured from falling to rising and rising to falling edges of ctm. the t cr and t cf rise- and fall-time parameters are measured at the 20% and 80% points. t as attn-to-stby power state delay C1 t cycle figure 46 t sa stby-to-attn power state delay C 0 t cycle figure 46 t asn attn/stby-to-nap power state delay C 8 t cycle figure 47 t asp attn/stby-to-pdn power state delay C 8 t cycle figure 47 1) this parameter also applies to a -800 or -711 part when operated with t cycle =3.33ns. 2) this parameter also applies to a -800 part when operated with t cycle =2.81ns. 3) t q,min and t q,max for other t cycle values can be interpolated between or extrapolated from the timings at the 3 specified t cycle values. table 22 timing characteristics (contd) parameter symbol limit values unit figure min. max.
data book 73 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 53 rsl timing - clock signals the cfm and cfmn are differential clock outputs used for receiving information on the dqa, dqb, row and col outputs. most timing is measured relative to the points where they cross. the t cycle parameter is measured from the falling cfm edge to the falling cfm edge. the t cl and t ch parameters are measured from falling to rising and rising to falling edges of cfm. the t cr and t cf rise- and fall-time parameters are measured at the 20% and 80% points. the t tr parameter specifies the phase difference that may be tolerated with respect to the ctm and cfm differential clock inputs (the ctm pair is always earlier). spt04239 20% cil v cih 50% 80% v cfmn cfm tr t cr v x- t cm v x+ v t cr t cf cf t cl t ch t cycle t ctm 80% 50% cih cil 20% v v ctmn cl t cycle t x- v cr cr t cf ch t x+ v v cm t cf t t
direct rdram 128/144-mbit (256k 16/18 32s) data book 74 2.00 rsl - receive timing figure 54 is a timing diagram which shows the detailed requirements for the rsl input signals on the channel. the dqa, dqb, row, and col signals are inputs which receive information transmitted by a direct rac on the channel. each signal is sampled twice per t cycle interval. the set/hold window of the sample points is t s / t h. the sample points are centered at the 0% and 50% points of a cycle, measured relative to the crossing points of the falling cfm clock edge. the set and hold parameters are measured at the v ref voltage point of the input transition. the t dr and t df rise- and fall-time parameters are measured at the 20% and 80% points of the input transition. figure 54 rsl timing - data signals for receive spt04240 20% dil v dih 80% v dqb dr t t s cfm 80% 50% cih cil 20% v v cfmn x- v x+ v v cm row col dqa t df t h t s h t t cycle 0.5 x even odd ref v
data book 75 2.00 direct rdram 128/144-mbit (256k 16/18 32s) rsl - transmit timing figure 55 is a timing diagram which shows the detailed requirements for the rsl output signals on the channel. the dqa and dqb signals are outputs to transmit information that is received by a direct rac on the channel. each signal is driven twice per t cycle interval. the beginning and end of the even transmit window is at the 75% point of the previous cycle and at the 25% point of the current cycle. the beginning and end of the odd transmit window is at the 25% point and at the 75% point of the current cycle. these transmit points are measured relative to the crossing points of the falling ctm clock edge. the size of the actual transmit window is less than the ideal t cycle /2, as indicated by the non-zero values of t q,min and t q,max . the t q parameters are measured at the 50% voltage point of the output transition. the t qr and t qf rise- and fall-time parameters are measured at the 20% and 80% points of the output transition. figure 55 rsl timing - data signals for transmit cmos - receive timing figure 56 is a timing diagram which shows the detailed requirements for the cmos input signals. the cmd and sio0 signals are inputs which receive information transmitted by a controller (or by another rdrams sio1 output. sck is the cmos clock signal driven by the controller. all signals are high true. spt04241 20% ql v qh 50% 80% v dqb qr t t q, max ctm 80% 50% cih cil 20% v v ctmn x- v x+ v v cm dqa t qf t cycle 0.25 x 0.75 x cycle t q, min t q, max t t q, min cycle 0.75 x t odd even
direct rdram 128/144-mbit (256k 16/18 32s) data book 76 2.00 the cycle time, high phase time, and low phase time of the sck clock are t cycle1 , t ch1 and t cl1 , all measured at the 50% level. the rise and fall times of sck, cmd, and sio0 are t dr1 and t df1 , measured at the 20% and 80% levels. the cmd signal is sampled twice per t cycle1 interval, on the rising edge (odd data) and the falling edge (even data). the set/hold window of the sample points is t s1 / t h1. the sck and cmd timing points are measured at the 50% level. the sio0 signal is sampled once per t cycle1 interval on the falling edge. the set/hold window of the sample points is t s2 / t h2. the sck and sio0 timing points are measured at the 50% level. figure 56 cmos timing - data signals for receive spt04242 20% il, cmos v ih, cmos 50% 80% v cmd dr2 t t s1 sck 80% 50% ih, cmos il, cmos 20% v v t df2 t h1 t cycle1 50% 20% v sio0 v 80% ih, cmos il, cmos t dr2 ch1 t cl1 t t h1 t s1 df1 t dr1 t t t s2 h2 even odd df2 t
data book 77 2.00 direct rdram 128/144-mbit (256k 16/18 32s) the sck clock is also used for sampling data on rsl inputs in one situation. figure 48 shows the pdn and nap exit sequences. if the psx field of the init register is one (see figure 27 ), then the pdn and nap exit sequences are broadcast; i.e. all rdrams that are in pdn or nap will perform the exit sequence. if the psx field of the init register is zero, then the pdn and nap exit sequences are directed; i.e. only one rdram that is in pdn or nap will perform the exit sequence. the address of that rdram is specified on the dqa[5:0] bus in the set hold window t s3 / t h3 around the rising edge of sck. this is shown in figure 57 . the sck timing point is measured at the 50% level, and the dqa[5:0] bus signals are measured at the v ref level. figure 57 cmos timing - device address for nap or pdn exit cmos - transmit timing figure 58 is a timing diagram which shows the detailed requirements for the cmos output signals. the sio0 signal is driven once per t cycle1 interval on the falling edge. the clock-to-output window is t q1,min / t q1,max. the sck and sio0 timing points are measured at the 50% level. the rise and fall times of sio0 are t qr1 and t qf1 , measured at the 20% and 80% levels. spt04243 20% dil v dih 80% v dqa(5:0) sck 80% 50% ih, cmos il, cmos 20% v v t h3 t s3 pdev v ref
direct rdram 128/144-mbit (256k 16/18 32s) data book 78 2.00 figure 58 cmos timing - data signals for transmit spt04244 20% ol, cmos v oh, cmos 50% 80% v sio0 sck 80% 50% ih, cmos il, cmos 20% v v il, cmos v 20% 50% ih, cmos v 80% sio1 or sio0 v ol, cmos sio1 oh, cmos 50% 20% 80% v sio0 or q1, max t hr, min t qr1 t t qf1 t dr1 t df1 prop1, max t prop1, min t qr1 t qf1 t
data book 79 2.00 direct rdram 128/144-mbit (256k 16/18 32s) figure 58 also shows the combinational path connecting sio0 to sio1 and the path connecting sio1 to sio0 (read data only). the t prop1 parameter specified this propagation delay. the rise and fall times of sio0 and sio1 inputs must be t dr1 and t df1 , measured at the 20% and 80% levels. the rise and fall times of sio0 and sio1 outputs are t qr1 and t qf1 , measured at the 20% and 80% levels. rsl - domain crossing window when read data is returned by the rdram, information must cross from the receive clock domain (cfm) to the transmit clock domain (ctm). the t tr parameter permits the cfm to ctm phase to vary through an entire cycle; i.e. there is no restriction on the alignment of these two clocks. a second parameter t dcw is needed in order to describe how the delay between a rd command packet and read data packet varies as a function of the t tr value. figure 59 shows this timing for five distinct values of t tr . case a ( t tr = 0) is what has been used throughout this document. the delay between the rd command and read data is t cac . as t tr varies from zero to t cycle (cases a through e), the command to data delay is ( t cac C t tr ). when the t tr value is in the range 0 to t dcw,max , the command to data delay can also be ( t cac C t tr C t cycle ). this is shown as cases a and b (the gray packets). similarly, when the t tr value is in the range ( t cycle + t dcw,min ) to t cycle , the command to data delay can also be ( t cac C t tr + t cycle ). this is shown as cases d and e (the gray packets). the rdram will work reliably with either the white or gray packet timing. the delay value is selected at initialization, and remains fixed thereafter.
direct rdram 128/144-mbit (256k 16/18 32s) data book 80 2.00 figure 59 rsl transmit - crossing read domains spa04245 cfm ctm cycle t tr t tr t = 0 = 0 tr t case a case a' ctm tr t case b' case b tr tr t t = = dcw, max t t dcw, max case c ctm t tr cycle tr t = 0.5 t * case d ctm tr t = tr t cycle t dcw, min t + case d' dcw, min cycle tr t = t + t case e' case e t tr cycle cycle tr tr t t t = = t ctm q(a1) rd a1 cac t tr t - tt cac - tr t + cycle t cac t - tr t + cac t - tr t cycle q(a1) q(a1) cac t - tr t t cac cac t - t - tr tr t - t cycle q(a1) - cac t cac t q(a1) cycle - tr tt tr t - q(a1) q(a1) q(a1) q(a1) col dqa/b dqa/b dqa/b dqa/b dqa/b dqa/b dqa/b dqa/b dqa/b
data book 81 2.00 direct rdram 128/144-mbit (256k 16/18 32s) timing parameters table 23 timing parameter summary parameter description min -40 -800 min -45 -800 min -45 -711 min -53 -600 max unit figure t rc row cycle time of rdram banks - the interval between rowa packets with act commands to the same bank. 28 28 28 28 C t cycle figure 15 figure 16 t ras ras -asserted time of rdram bank - the interval between rowa packet with act command and next rowr packet with prer 1) command to the same bank. 20 20 20 20 64 m s 2) t cycle figure 15 figure 16 t rp row precharge time of rdram banks - the interval between rowr packet with prer a command and next rowa packet with act command to the same bank. 8888C t cycle figure 15 figure 16 t pp precharge-to-precharge time of rdram device - the interval between successive rowr packets with prer a commands to any banks of the same device. 8888C t cycle figure 12 t rr ras -to-ras time of rdram device - the interval between successive rowa packets with act commands to any banks of the same device. 8888C t cycle figure 13 t rcd ras -to-cas delay - the interval from rowa packet with act command to colc packet with rd or wr command). note - the ras -to-cas delay seen by the rdram core ( t rcd-c ) is equal to t rcd-c = 1 + t rcd because of differences in the row and column paths through the rdram interface. 7977C t cycle figure 15 figure 16 t cac cas access delay - the interval from rd command to q read data. the equation for t cac is given in the tparm register in figure 39 . 888812 t cycle figure 4 figure 39 t cwd cas write delay (interval from wr command to d write data. 66666 t cycle figure 4 t cc cas -to-cas time of rdram bank - the interval between successive colc commands). 4444- t cycle figure 15 figure 16 t packet length of rowa, rowr, colc, colm or colx packet. 44444 t cycle figure 3 t rtr interval from colc packet with wr command to colc packet which causes retire, and to colm packet with bytemask. 8888- t cycle figure 17 t offp the interval (offset) from colc packet with rda command, or from colc packet with retire command (after wra automatic precharge), or from colc packet with prec command, or from colx packet with prex command to the equivalent rowr packet with prer. the equation for t offp is given in the tparm register in figure 39 . 44444 t cycle figure 14 figure 39
direct rdram 128/144-mbit (256k 16/18 32s) data book 82 2.00 t rdp interval from last colc packet with rd command to rowr packet with prer. 4444 C t cycle figure 15 t rtp interval from last colc packet with automatic retire command to rowr packet with prer. 4444C t cycle figure 16 1) or equivalent prec or prex command. see figure 14 . 2) this is a constraint imposed by the core, and is therefore in units of m s rather than t cycle . table 24 absolute maximum ratings parameter symbol limit values unit min. max. voltage applied to any rsl or cmos pin with respect to gnd v i,abs C0.3 v dd + 0.3 v voltage on v dd and v dda with respect to gnd v dd,abs , v dda,abs C0.5 v dd +1.0 v storage temperature t store C 50 100 c table 23 timing parameter summary (contd) parameter description min -40 -800 min -45 -800 min -45 -711 min -53 -600 max unit figure
data book 83 2.00 direct rdram 128/144-mbit (256k 16/18 32s) i dd - supply current profile table 25 supply current profile rdram blocks consuming power 1) 1) the cmos interface consumes power in all power states. i dd value limit values unit max. -800 max. -711 max. -600 self-refresh only for init.lsr = 0 i dd,pdn 3000 3000 3000 m a t/rclk-nap i dd,nap 444ma t/rclk, row-demux i dd,stby 100 95 90 ma t/rclk, row-demux, col-demux i dd,attn 150 145 140 ma t/rclk, row-demux, col-demux, dq- demux, 1 wr-senseamp, 4 act-bank i dd,attn-w 575/635 2) 515/570 450/495 2) 2) x16/x18 rdram data width. ma t/rclk, row-demux, col-demux, dq- mux, 1 rd-senseamp, 4 act-bank 3) 3) this does not include the i ol sink current. the rdram dissipates i ol v ol in each output driver when a logic one is driven. i dd,attn-r 520/575 2) 470/520 410/450 ma
direct rdram 128/144-mbit (256k 16/18 32s) data book 84 2.00 capacitance and inductance figure 60 shows the equivalent load circuit of the rsl and cmos pins. the circuit models the load that the device presents to the channel. figure 60 equivalent load circuit for rsl pins spt04246 i r i c l i pad dqa, dqb, rq pin gnd pin pad c r i i l i gnd pin ctm, ctmn, pad c i l i gnd pin sck, cmd pin pad c i gnd pin sio0, sio1 pin cfm, cfmn pin , cmos , cmos , cmos l i , cmos, sio
data book 85 2.00 direct rdram 128/144-mbit (256k 16/18 32s) this circuit does not include pin coupling effects that are often present in the packaged device. because coupling effects make the effective single-pin inductance l i , and capacitance c i , a function of neighboring pins, these parameters are intrinsically data-dependent. for purposes of specifying the device electrical loading on the channel, the effective l i and c i are defined as the worst-case values over all specified operating conditions. l i is defined as the effective pin inductance based on the device pin assignment. because the pad assignment places each rsl signal adjacent to an ac ground (a gnd or v dd pin), the effective inductance must be defined based on this configuration. therefore, l i assumes a loop with the rsl pin adjacent to an ac ground. c i is defined as the effective pin capacitance based on the device pin assignment. it is the sum of the effective package pin capacitance and the io pad capacitance. table 26 rsl pin parasitics parameter and conditions - rsl pins symbol limit values unit min. max. rsl effective input inductance l i C4.0 nh mutual inductance between any dqa or dqb rsl signals. l 12 C0.2 nh mutual inductance between any row or col rsl signals. C0.6 nh difference in l i value between any rsl pins of a single device. d l i C1.8 nh rsl effective input capacitance 1) -800 rsl effective input capacitance 1) -711 rsl effective input capacitance 1) -600 1) this value is a combination of the device io circuitry and package capacitances. c i 2.0 2.0 2.0 2.4 2.4 2.6 pf pf pf mutual capacitance between any rsl signals. c 12 C0.1 pf difference in c i value between average of ctm/cfm and any rsl pins of a single device. d c i C0.06 pf rsl effective input resistance r i 415 w table 27 cmos pin parasitics parameter and conditions - cmos pins symbol limit values unit min. max. cmos effective input inductance l i ,cmos C8.0nh cmos effective input capacitance (sck,cmd) 1) 1) this value is a combination of the device io circuitry and package capacitances. c i ,cmos 1.7 2.1 pf cmos effective input capacitance (sio1, sio0) 1) c i ,cmos,sio C7.0pf
direct rdram 128/144-mbit (256k 16/18 32s) data book 86 2.00 center-bonded fbga package figure 61 shows the form and dimensions of the recommended package for the center-bonded csp device class. figure 61 center-bonded fbga package table 28 lists the numerical values corresponding to dimensions shown in figure 61 . ab cde f ghj 1 2 3 4 5 6 7 d a e1 d e e1 8 e2 to p bottom bottom bottom 9 10 11 2
data book 87 2.00 direct rdram 128/144-mbit (256k 16/18 32s) table 28 center-bonded fbga package dimensions parameter symbol limit values unit min. max. ball pitch (x-axis) e1 1.00 1.00 mm ball pitch (y-axis) e2 0.8 0.8 mm package body length a 10.9 11.1 mm package body width d 10.4 10.6 mm package total thickness e 0.65 1.05 mm ball height e1 0.18 0.35 mm ball diameter d 0.3 0.4 mm
direct rdram 128/144-mbit (256k 16/18 32s) data book 88 2.00 glossary of terms act activate command from av field. activate to access a row and place in sense amp. adjacent two rdram banks which share sense amps (also called doubled banks). asym cca register field for rsl v ol / v oh . at tn power state - ready for row/col packets. at tn r power state - transmitting q packets. at tn w power state - receiving d packets. av opcode field in row packets. bank a block of 2 rbit 2 cbit storage cells in the core of the rdram. bc bank address field in colc packet. bbit cnfga register field - # bank address bits. broad cast an operation executed by all rdrams. br bank address field in row packets. bubble idle cycle(s) on rdram pins needed because of a resource constraint. byt cnfgb register field - 8/9 bits per byte. bx bank address field in colx packet. c column address field in colc packet. cal calibrate ( i ol ) command in xop field. cbit cnfgb register field - # column address bits. cca control register - current control a. ccb control register - current control b. cfm,cfmn clock pins for receiving packets. channel row/col/dq pins and external wires. clrr clear reset command from sop field. cmd cmos pin for initialization/power control. cnfga control register with configuration fields. cnfgb control register with configuration fields. col pins for column-access control. col colc,colm,colx packet on col pins. colc column operation packet on col pins. colm write mask packet on col pins. column rows in a bank or activated row in sense amps have 2 cbit dualocts column storage. command a decoded bit-combination from a field. colx extended operation packet on col pins.
data book 89 2.00 direct rdram 128/144-mbit (256k 16/18 32s) controller a logic-device which drives the row/col /dq wires for a channel of rdrams. cop column opcode field in colc packet. core the banks and sense amps of an rdram. ctm,ctmn clock pins for transmitting packets. current control periodic operations to update the proper i ol value of rsl output drivers. d write data packet on dq pins. dbl cnfgb register field - doubled-bank. dc device address field in colc packet. device an rdram on a channel. devid control register with device address that is matched against dr, dc, and dx fields. dm device match for row packet decode. doubled-bank rdram with shared sense amp. dq dqa and dqb pins. dqa pins for data byte a. dqb pins for data byte b. dqs napx register field - pdn/nap exit. dr,dr4t,dr4f device address field and packet framing fields in rowa and rowr packets. dualoct 16 bytes - the smallest addressable datum. dx device address field in colx packet. field a collection of bits in a packet. init control register with initialization fields. initialization configuring a channel of rdrams so they are ready to respond to transactions. lsr cnfga register field - low-power self-refresh. m mask opcode field (colm/colx packet). ma field in colm packet for masking byte a. mb field in colm packet for masking byte b. msk mask command in m field. mver control register - manufacturer id. nap power state - needs sck/cmd wakeup. napr nap command in rop field. naprc conditional nap command in rop field. napxa napx register field - nap exit delay a. napxb napx register field - nap exit delay b. nocop no-operation command in cop field.
direct rdram 128/144-mbit (256k 16/18 32s) data book 90 2.00 norop no-operation command in rop field. noxop no-operation command in xop field. nsr init register field- nap self-refresh. packet a collection of bits carried on the channel. pdn power state - needs sck/cmd wakeup. pdnr powerdown command in rop field. pdnxa control register - pdn exit delay a. pdnxb control register - pdn exit delay b. pin efficiency the fraction of non-idle cycles on a pin. pre prec,prer,prex precharge commands. prec precharge command in cop field. precharge prepares sense amp and bank for activate. prer precharge command in rop field. prex precharge command in xop field. psx init register field - pdn/nap exit. psr init register field - pdn self-refresh. pver cnfgb register field - protocol version. q read data packet on dq pins. r row address field of rowa packet. rbit cnfgb register field - # row address bits. rd/rda read (/precharge) command in cop field. read operation of accessing sense amp data. receive moving information from the channel into the rdram (a serial stream is demuxed). refa refresh-activate command in rop field. refb control register - next bank (self-refresh). refbit cnfga register field - ignore bank bits (for refa and self-refresh). refp refresh-precharge command in rop field. refr control register - next row for refa. refresh periodic operations to restore storage cells. retire the automatic operation that stores write buffer into sense amp after wr command. rlx rlxc,rlxr,rlxx relax commands. rlxc relax command in cop field. rlxr relax command in rop field. rlxx relax command in xop field. rop row-opcode field in rowr packet.
data book 91 2.00 direct rdram 128/144-mbit (256k 16/18 32s) row 2 cbit dualocts of cells (bank/sense amp). row pins for row-access control row rowa or rowr packets on row pins. rowa activate packet on row pins. rowr row operation packet on row pins. rq alternate name for row/col pins. rsl rambus signaling levels. sam sample ( i ol ) command in xop field. sa serial address packet for control register transactions w/ sa address field. sbc serial broadcast field in srq. sck cmos clock pin. sd serial data packet for control register transactions w/ sd data field. sdev serial device address in srq packet. sdevid init register field - serial device id. self-refresh refresh mode for pdn and nap. sense amp fast storage that holds copy of banks row. setf set fast clock command from sop field. setr set reset command from sop field. sint serial interval packet for control register read/write transactions. sio0,sio1 cmos serial pins for control registers. sop serial opcode field in srq. srd serial read opcode command from sop. srp init register field - serial repeat bit. srq serial request packet for control register read/write transactions. stby power state - ready for row packets. sver control register - stepping version. swr serial write opcode command from sop. tcas tclscas register field - t cas core delay. tcls tclscas register field - t cls core delay. tclscas control register - t cas and t cls delays. tcycle control register - t cycle delay. tdac control register - t dac delay. test77 control register - for test purposes. test78 control register - for test purposes. trdly control register - t rdly delay. transaction row,col,dq packets for memory access.
direct rdram 128/144-mbit (256k 16/18 32s) data book 92 2.00 transmit moving information from the rdram onto the channel (parallel word is muxed). wr/wra write (/precharge) command in cop field. write operation of modifying sense amp data. xop extended opcode field in colx packet
direct rdram 128/144-mbit (256k 16/18 32s) data book 93 2.00

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